AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
-
Updated
Aug 27, 2026 - SystemVerilog
#
axi
Here are 175 public repositories matching this topic...
Code generation tool for control and status registers
asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb systemrdl register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents
-
Updated
Aug 16, 2026 - Ruby
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
spi-interface fpga verilog sd-card sdio wishbone verilog-components verilator axi emmc wishbone-bus sd-interface
-
Updated
Aug 10, 2026 - Verilog
A Fast, Low-Overhead On-chip Network
-
Updated
Sep 1, 2026 - SystemVerilog
Network on Chip Implementation written in SytemVerilog
-
Updated
Aug 27, 2022 - SystemVerilog
Control and status register code generator toolchain
asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model
-
Updated
Sep 1, 2026 - Python
Simple single-port AXI memory interface
-
Updated
Jun 7, 2024 - SystemVerilog
OPAE porting to Xilinx FPGA devices.
-
Updated
Aug 5, 2020 - Coq
RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction.
-
Updated
Mar 13, 2025 - Verilog
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
simulation vhdl verilog questasim ghdl avalon memory-model test-bench pli verilog-components verilator axi nvc dpi-c cosimulation vivado-simulator verilog-testbenches
-
Updated
Feb 2, 2026 - VHDL
This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects
protocol verification eda rtl verilog systemverilog alu vlsi modelsim uvm verilog-hdl axi apb ahb verilog-project vlsi-design design-verification vlsi-project axi-lite system-verilog-testbench
-
Updated
May 23, 2026 - SystemVerilog
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
spi-interface fpga spi altera verilog-hdl xilinx-fpga xilinx-vivado verilog-components axi verilog-snippets spi-hdl spi-ip-core spi-pld spi-fpga verilog-spi axi-interfaces bit-oriented-spi soft-spi hard-spi dragster-spi
-
Updated
Nov 21, 2017 - Verilog
XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA
fpga vivado pcie axi ddr4 xdma innova2 xcku15p mnv303212a innova-2-flex mnv303212a-adlt 4xc7a16683 01pg974 pcie-xdma
-
Updated
Mar 7, 2024 - Tcl
Add this topic to your repo
To associate your repository with the axi topic, visit your repo's landing page and select "manage topics."