SoC / RTL Engineer | Compute Accelerators | Subsystem Architecture
I design and implement high-performance hardware subsystems from microarchitecture to FPGA validation.
My work focuses on compute-intensive accelerators, memory-bound systems, and deterministic pipelines.
- Built QR Decomposition accelerator (CORDIC-based Givens rotations)
- Achieved 101 kQRD/s @ 245.76 MHz on Xilinx UltraScale+ FPGA
- Designed memory-driven architecture with II = 2 (bandwidth-limited)
Currently working on hardware acceleration for digital beamforming systems.
- Compute Accelerators (QRD / DSP pipelines)
- Hardware Microarchitecture
- Memory Systems & Dataflow Design
- SoC / AXI-based Integration
- FPGA Prototyping (UltraScale+)
RTL & Design
- SystemVerilog, Verilog, VHDL
Modeling & Software
- MATLAB, Python, C, SystemC
EDA & Tools
- Vivado, Cadence Genus, Xcelium, JasperGold
Platforms
- Xilinx UltraScale+ (ZCU216, ZCU111, KV260)
High-throughput hardware accelerator using CORDIC-based Givens rotations.
- Fixed-latency pipeline
- Memory-bound architecture
- FPGA validated implementation
- Email: [email protected]
- LinkedIn: https://www.linkedin.com/in/vnay01
- Interested in system architecture and high-performance hardware design
- Background in DSP, SoC design, and accelerator architectures