Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
Traceable datasheet-to-SPICE model generation for power MOSFETs and diodes, with browser extraction and validation benchmarks.
This repository serves as an archive of all the knowledge I acquired and encountered during the VSD-Advanced Physical Design workshop. I have utilised several snippets to demonstrate the ideas I gathered in the lectures and the outcomes of my lab module.
4-bit ALU RTL to Gate-Level Synthesis using Yosys + ABC on EDA Playground
A hands-on implementation of physical design for a Serial Peripheral Interface (SPI) controller — progressing from RTL Verilog through synthesis, placement, static timing analysis, routing, DRC, LVS, and GDSII generation using the open-source Qflow EDA toolchain with OSU018 standard cell library.
RTL-to-GDSII physical design flow of PicoRV32a RISC-V processor using OpenLANE and Sky130 PDK. Completed under NASSCOM FutureSkills Prime program. Synthesis, floorplan, placement, CTS, routing, DRC/LVS clean, GDSII generated.
Parameterized asynchronous CDC FIFO IP: gray-code pointers, a sweepable N-flop synchronizer, IEEE 1801 UPF low-power intent, SymbiYosys formal proofs, and a 60-config Yosys/OpenSTA PPA sweep on SkyWater Sky130. Fully open-source and reproducible.
Complete RTL-to-GDSII physical design flow of an 8-bit ALU using OpenLane and Sky130 PDK. Includes synthesis, floorplanning, placement, CTS, routing, DRC/LVS signoff, and multi-corner STA.
int8 serial multiply accumulate for Tiny Tapeout sky130, RTL to GDS on open tools, mutation gated formal proof, one hash sealed
RTL-to-GDS physical design of a parameterized MAC accelerator using open-source ASIC tools (Yosys, OpenLane, Sky130)
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