👋 Hi, I'm Han Wang

🔬 Design Verification Engineer  |  ⌨️ Vim Enthusiast

SystemVerilog & UVM syntax highlighting and indent plugin for Vim/Neovim. Fixes indentation edge cases, adds UVM highlighting, and completes matchit pairs.

Signal/variable tracing plugin for Verilog/SystemVerilog/UVM — traces declarations, drivers and loads across your project, with hierarchy trees and Mermaid topology export.

Sparse recovery / compressed sensing research — paper code will be released here.

• 📚 博通 Jericho+Ramon 与 Tomahawk 技术架构与区别详解 — 2026-10-18
• 📚 UVM接口信号同步机制 — 2026-08-19
• 💡 UVM调试功能全解析 — 2026-08-19
• 💡 UVM Sequence 学习记录 — 2026-08-01
• 📚 Common 分解 — 2026-08-01

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• 🔬 Design Verification Engineer — focused on SystemVerilog / UVM chip functional verification
• ⌨️ Vim power user — writes code in Vim daily and builds plugins (systemverilog.vim, sv_trace)
• 📚 Tooling tinkerer — from Vim config to workflow automation, I script away the boring stuff
• 🌱 Currently learning — better verification methodologies & advanced editor skills

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