- 👋 Hi, I’m @sociter
- 👀 I’m interested in Design Verification and Python
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rggen
rggen PublicForked from rggen/rggen
Code generation tool for configuration and status registers
Ruby
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open-register-design-tool
open-register-design-tool PublicForked from Juniper/open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Verilog
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eda-sim-ai
eda-sim-ai PublicForked from cike128/eda-sim
FROM: https://mp.weixin.qq.com/s/9qUIKQYhLRh7TGfIjJQRhw
Python
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AI_Formal_Counter
AI_Formal_Counter PublicForked from gokeshenzhen/AI_Formal_Counter
FRROM:
SystemVerilog
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