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1. Commits on Dec 16, 2021

   • Use arm64's fmax/fmin instructions in Wasm

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2. Commits on Aug 3, 2021

   • Add a new pattern to instruction selector to utilize UMULL supported by ARM64

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     hyjorc1

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   • Add new patterns to instruction selector to utilize AND/EOR/ORR-with-shift supported by ARM64

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3. Commits on Jul 30, 2021

   • Add Pre/Post-Indexed Address Mode to Air for ARM64

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4. Commits on Jul 20, 2021

   • Add ARM64 EON opcode and select it in AIR

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5. Commits on Jul 13, 2021

   • Add a new Air::Arg kind ZeroReg to let AIR recognise the new instructions/forms accepting zero register in ARM64

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6. Commits on Jul 12, 2021

   • Add SMNEGL, UMNEGL, UMADDL, and UMSUBL for ARM64 and select this instruction in Air

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7. Commits on Jul 9, 2021

   • Add Air opcode add/sub-and-shift for ARM64 and select this instruction in Air

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8. Commits on Jul 6, 2021

   • Fix instruction check failure of UBFX and SBFIZ in testb3 due to the speculative fix in bug 227554

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9. Commits on Jul 1, 2021

   • Add a new pattern to instruction selector to use EXTR supported by ARM64

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10. Commits on Jun 29, 2021

    • Add a new pattern to instruction selector to use SBX and SBFIZ supported by ARM64

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    • Add a new pattern to instruction selector to use BIC supported by ARM64

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11. Commits on Jun 24, 2021

    • Add a new pattern to instruction selector to utilize BFI supported by ARM64

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12. Commits on Jun 23, 2021

    • Add a new pattern to instruction selector to utilize UBFIZ supported by ARM64

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13. Commits on Jun 22, 2021

    • Add a new pattern to instruction selector to utilize SMADDL supported by ARM64

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14. Commits on Jun 21, 2021

    • Add a new pattern to instruction selector to utilize SMSUBL supported by ARM64

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15. Commits on Jun 17, 2021

    • Add a new pattern to instruction selector to utilize UBFX supported by ARM64

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16. Commits on Jun 16, 2021

    • Add Air opcode sub32/64(Reg, Imm, Reg) form for ARM64 and select this instruction in Air

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    • Unreviewed, reverting r278846.

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17. Commits on Jun 14, 2021

    • Add Air opcode sub32/64(Reg, Imm, Reg) form for ARM64 and select this instruction in Air

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18. Commits on Jun 11, 2021

    • Air ARM64 sub32 opcode should indicate that it zero-extends its result

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19. Commits on Nov 28, 2020

    • [JSC] Use ARM atomic ops in wasm

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      Constellation

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20. Commits on Jul 1, 2020

    • Rename zeroExtend32ToPtr to zeroExtend32ToWord

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21. Commits on Jul 27, 2019

    • [X86] Emit BT instruction for shift + mask in B3

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      Justin Michaud

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22. Commits on Jul 11, 2019

    • Add b3 macro lowering for CheckMul on arm64

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      Justin Michaud

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23. Commits on Jul 1, 2019

    • Unreviewed, rolling out r246946.

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24. Commits on Jun 28, 2019

    • Add b3 macro lowering for CheckMul on arm64

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      Justin Michaud

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25. Commits on Feb 15, 2019

    • lowerStackArgs should lower Lea32/64 on ARM64 to Add

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      saambarati

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26. Commits on Jul 26, 2017

    • WebAssembly: generate smaller binaries

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27. Commits on May 19, 2017

    • B3::Value::effects() says that having a fence range implies the fence bit, but on x86_64 we lower loadAcq/storeRel to load/store so the store-before-load fence bit orderings won't be honored

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      Filip Pizlo

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28. Commits on Mar 30, 2017

    • Air should support linear scan for optLevel<2

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      Filip Pizlo

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29. Commits on Mar 20, 2017

    • Graph coloring should use coalescable moves when spilling

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      Filip Pizlo

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30. Commits on Mar 10, 2017

    • B3 should have comprehensive support for atomic operations

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      Filip Pizlo

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31. Commits on Dec 23, 2016

    • Add BitOr for floating points to B3

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      kmiller68

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32. Commits on Nov 17, 2016

    • Add support for rotate in B3 and the relevant assemblers

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      kmiller68

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