Pinned Loading

1. RTL-Design RTL-Design Public

   A collection of Verilog RTL designs and testbenches developed while learning digital design, verification, and FPGA fundamentals.

   Verilog

2. C-Language C-Language Public

   C

3. Process-Communicate-Manager Process-Communicate-Manager Public

   C

4. Process-Scheduling-Simulator-with-Priority-Adjustment Process-Scheduling-Simulator-with-Priority-Adjustment Public

   C

5. BreastCancer_ML_Model BreastCancer_ML_Model Public

   Jupyter Notebook

6. Cpp Cpp Public

   Catching up & learning

   C++