This section contains HLS C/C++ Kernel Examples.
Examples Table
| Example | Description | Key Concepts / Keywords |
|---|---|---|
| array_partition/ | This is a simple example of matrix multiplication (Row x Col) to demonstrate how to achieve better performance by array partitioning, using HLS kernel in Vitis Environment. | Key Concepts - Kernel Optimization - HLS C Kernel - Array Partition Keywords - #pragma HLS ARRAY_PARTITION - complete |
| burst_rw/ | This is simple example of using AXI4-master interface for burst read and write | Key Concepts - burst access Keywords - memcpy - max_read_burst_length - max_write_burst_length |
| critical_path/ | This example shows a normal coding style which could lead to critical path issue and design will give degraded timing. Example also contains better coding style which can improve design timing. | Key Concepts - Critical Path handling - Improve Timing |
| custom_datatype/ | This is simple example of RGB to HSV conversion to demonstrate Custom DATA Type usages in C Based Kernel. Xilinx HLS Compiler Supports Custom Data Type to use for operation as well as Memory Interface between Kernel and Global Memory. | Key Concepts - Custom Datatype Keywords - struct - #pragma HLS data_pack - #pragma HLS LOOP_TRIPCOUNT |
| dataflow_stream/ | This is simple example of vector addition to demonstrate Dataflow functionality of HLS. HLS Dataflow allows user to schedule multiple task together to achieve higher throughput. | Key Concepts - Task Level Parallelism Keywords - dataflow - hls::stream |
| dataflow_stream_array/ | This is simple example of Multiple Stages Vector Addition to demonstrate Array of Stream usage in HLS C Kernel Code. | Key Concepts - Array of Stream Keywords - dataflow - hls::stream |
| dependence_inter/ | This Example demonstrates the HLS pragma 'DEPENDENCE'.Using 'DEPENDENCE' pragma, user can provide additional dependency details to the compiler by specifying if the dependency in consecutive loop iterations on buffer is true/false, which allows the compiler to perform unrolling/pipelining to get better performance. | Key Concepts - Inter Dependence Keywords - DEPENDENCE - inter - WAR |
| gmem_2banks/ | This example of 2ddr is to demonstrate how to use multiple ddr and create buffers in each DDR. | Key Concepts - Multiple Banks Keywords - max_memory_ports - sp - connectivity |
| kernel_chain/ | This is a kernel containing the cascaded Matrix Multiplication using dataflow. ap_ctrl_chain is enabled for this kernel to showcase how multiple enqueue of Kernel calls can be overlapped to give higher performance. ap_ctrl_chain allow kernel to start processing of next kernel operation before completing the current kernel operation. | Key Concepts - ap_ctrl_chain - PLRAM |
| kernel_global_bandwidth/ | Bandwidth test of global to local memory. | |
| lmem_2rw/ | This is simple example of vector addition to demonstrate how to utilize both ports of Local Memory. | Key Concepts - Kernel Optimization - 2port BRAM Utilization - two read/write Local Memory Keywords - #pragma HLS UNROLL FACTOR=2 |
| loop_pipeline/ | This example demonstrates how loop pipelining can be used to improve the performance of a kernel. | Key Concepts - Kernel Optimization - Loop Pipelining Keywords - pragma HLS PIPELINE |
| loop_reorder/ | This is a simple example of matrix multiplication (Row x Col) to demonstrate how to achieve better pipeline II factor by loop reordering. | Key Concepts - Kernel Optimization - Loop reorder to improve II Keywords - #pragma HLS PIPELINE - #pragma HLS ARRAY_PARTITION |
| partition_cyclicblock/ | This example shows how to use array block and cyclic partitioning to improve performance of a kernel | Key Concepts - Kernel Optimization - Array Partitioning - Block Partition - Cyclic Partition Keywords - #pragma HLS ARRAY_PARTITION - cyclic - block - factor - dim |
| plram_access/ | This example shows the usage of PLRAM and how to use it with simple matrix multiplication (Row x Col). | Key Concepts - Vitis Memory Hierarchy - PLRAMs Keywords - PLRAM |
| shift_register/ | This example demonstrates how to shift values in registers in each clock cycle | Key Concepts - Kernel Optimization - Shift Register - FIR Keywords - #pragma HLS ARRAY_PARTITION |
| systolic_array/ | This is a simple example of matrix multiplication (Row x Col) to help developers learn systolic array based algorithm design. Note : Systolic array based algorithm design is well suited for FPGA. | |
| wide_mem_rw/ | This is simple example of vector addition to demonstrate Wide Memory Access using ap_uint<512> data type. Based on input argument type, V++ compiler will figure our the memory datawidth between Global Memory and Kernel. For this example, ap_uint<512> datatype is used, so Memory datawidth will be 16 x (integer bit size) = 16 x 32 = 512 bit. | Key Concepts - Kernel to DDR - wide memory access - burst read and write Keywords - ap_uint<> - ap_int.h |