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Commits on Feb 27, 2018

• Update README.md

  hannahvsawiuk

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Commits on May 3, 2017

• Update README.md

  hannahvsawiuk

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Commits on May 2, 2017

• stage_tb.v

  hannahvsawiuk

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• stage1.v

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• shift_tb.v

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• shift.v

  hannahvsawiuk

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• regfile_tb.v

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• regfile.v

  hannahvsawiuk

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• top.v

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• Decoder_tb.v

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• Decoder.v

  hannahvsawiuk

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• Datapath_tb.v

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• Datapath.v

  hannahvsawiuk

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• ALU_tb.v

  hannahvsawiuk

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• CPU_tb.v

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• CPU.v

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• FSM_tb.v

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• FSM Controller for RISC machine

  hannahvsawiuk

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• Create ALU testbench.v

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• ALU

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• Update README.md

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• Initial commit

  hannahvsawiuk

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