Skip to content

Commit 87903ea

Browse files
author
Jim Wilson
committed
Fix bugs with float compare and Inf operands.
sim/aarch64/ * simulator.c (set_flags_for_float_compare): Add code to handle Inf. Add comment to document NaN issue. (set_flags_for_double_compare): Likewise. sim/testsuite/sim/aarch64/ * fcmp.s: New.
1 parent f0d19df commit 87903ea

4 files changed

Lines changed: 184 additions & 0 deletions

File tree

sim/aarch64/ChangeLog

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,9 @@
1+
2016-12-21 Jim Wilson <[email protected]>
2+
3+
* simulator.c (set_flags_for_float_compare): Add code to handle Inf.
4+
Add comment to document NaN issue.
5+
(set_flags_for_double_compare): Likewise.
6+
17
2016-12-13 Jim Wilson <[email protected]>
28

39
* simulator.c (NEG, POS): Move before set_flags_for_add64.

sim/aarch64/simulator.c

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8468,8 +8468,22 @@ set_flags_for_float_compare (sim_cpu *cpu, float fvalue1, float fvalue2)
84688468
{
84698469
uint32_t flags;
84708470

8471+
/* FIXME: Add exception raising. */
84718472
if (isnan (fvalue1) || isnan (fvalue2))
84728473
flags = C|V;
8474+
else if (isinf (fvalue1) && isinf (fvalue2))
8475+
{
8476+
/* Subtracting two infinities may give a NaN. We only need to compare
8477+
the signs, which we can get from isinf. */
8478+
int result = isinf (fvalue1) - isinf (fvalue2);
8479+
8480+
if (result == 0)
8481+
flags = Z|C;
8482+
else if (result < 0)
8483+
flags = N;
8484+
else /* (result > 0). */
8485+
flags = C;
8486+
}
84738487
else
84748488
{
84758489
float result = fvalue1 - fvalue2;
@@ -8540,8 +8554,22 @@ set_flags_for_double_compare (sim_cpu *cpu, double dval1, double dval2)
85408554
{
85418555
uint32_t flags;
85428556

8557+
/* FIXME: Add exception raising. */
85438558
if (isnan (dval1) || isnan (dval2))
85448559
flags = C|V;
8560+
else if (isinf (dval1) && isinf (dval2))
8561+
{
8562+
/* Subtracting two infinities may give a NaN. We only need to compare
8563+
the signs, which we can get from isinf. */
8564+
int result = isinf (dval1) - isinf (dval2);
8565+
8566+
if (result == 0)
8567+
flags = Z|C;
8568+
else if (result < 0)
8569+
flags = N;
8570+
else /* (result > 0). */
8571+
flags = C;
8572+
}
85458573
else
85468574
{
85478575
double result = dval1 - dval2;

sim/testsuite/sim/aarch64/ChangeLog

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,7 @@
1+
2016-12-21 Jim Wilson <[email protected]>
2+
3+
* fcmp.s: New.
4+
15
2016-12-13 Jim Wilson <[email protected]>
26

37
* testutils.inc (pass): Move .Lpass to start.

sim/testsuite/sim/aarch64/fcmp.s

Lines changed: 146 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,146 @@
1+
# mach: aarch64
2+
3+
# Check the FP compare instructions: fcmps, fcmpzs, fcmpes, fcmpzes, fcmpd,
4+
# fcmpzd, fcmped, fcmpzed.
5+
# For 1 operand compares, check 0, 1, -1, +Inf, -Inf.
6+
# For 2 operand compares, check 1/1, 1/-2, -1/2, +Inf/+Inf, +Inf/-Inf.
7+
# FIXME: Check for qNaN and sNaN when exception raising support added.
8+
9+
.include "testutils.inc"
10+
11+
start
12+
fmov s0, wzr
13+
fcmp s0, #0.0
14+
bne .Lfailure
15+
fcmpe s0, #0.0
16+
bne .Lfailure
17+
fmov d0, xzr
18+
fcmp d0, #0.0
19+
bne .Lfailure
20+
fcmpe d0, #0.0
21+
bne .Lfailure
22+
23+
fmov s0, #1.0
24+
fcmp s0, #0.0
25+
blo .Lfailure
26+
fcmpe s0, #0.0
27+
blo .Lfailure
28+
fmov d0, #1.0
29+
fcmp d0, #0.0
30+
blo .Lfailure
31+
fcmpe d0, #0.0
32+
blo .Lfailure
33+
34+
fmov s0, #-1.0
35+
fcmp s0, #0.0
36+
bpl .Lfailure
37+
fcmpe s0, #0.0
38+
bpl .Lfailure
39+
fmov d0, #-1.0
40+
fcmp d0, #0.0
41+
bpl .Lfailure
42+
fcmpe d0, #0.0
43+
bpl .Lfailure
44+
45+
fmov s0, #1.0
46+
fmov s1, wzr
47+
fdiv s0, s0, s1
48+
fcmp s0, #0.0
49+
blo .Lfailure
50+
fcmpe s0, #0.0
51+
blo .Lfailure
52+
fmov d0, #1.0
53+
fmov d1, xzr
54+
fdiv d0, d0, d1
55+
fcmp d0, #0.0
56+
blo .Lfailure
57+
fcmpe d0, #0.0
58+
blo .Lfailure
59+
60+
fmov s0, #-1.0
61+
fmov s1, wzr
62+
fdiv s0, s0, s1
63+
fcmp s0, #0.0
64+
bpl .Lfailure
65+
fcmpe s0, #0.0
66+
bpl .Lfailure
67+
fmov d0, #-1.0
68+
fmov d1, xzr
69+
fdiv d0, d0, d1
70+
fcmp d0, #0.0
71+
bpl .Lfailure
72+
fcmpe d0, #0.0
73+
bpl .Lfailure
74+
75+
fmov s0, #1.0
76+
fmov s1, #1.0
77+
fcmp s0, s1
78+
bne .Lfailure
79+
fcmpe s0, s1
80+
bne .Lfailure
81+
fmov d0, #1.0
82+
fmov d1, #1.0
83+
fcmp d0, d1
84+
bne .Lfailure
85+
fcmpe d0, d1
86+
bne .Lfailure
87+
88+
fmov s0, #1.0
89+
fmov s1, #-2.0
90+
fcmp s0, s1
91+
blo .Lfailure
92+
fcmpe s0, s1
93+
blo .Lfailure
94+
fmov d0, #1.0
95+
fmov d1, #-2.0
96+
fcmp d0, d1
97+
blo .Lfailure
98+
fcmpe d0, d1
99+
blo .Lfailure
100+
101+
fmov s0, #-1.0
102+
fmov s1, #2.0
103+
fcmp s0, s1
104+
bpl .Lfailure
105+
fcmpe s0, s1
106+
bpl .Lfailure
107+
fmov d0, #-1.0
108+
fmov d1, #2.0
109+
fcmp d0, d1
110+
bpl .Lfailure
111+
fcmpe d0, d1
112+
bpl .Lfailure
113+
114+
fmov s0, #1.0
115+
fmov s1, wzr
116+
fdiv s0, s0, s1
117+
fcmp s0, s0
118+
bne .Lfailure
119+
fcmpe s0, s0
120+
bne .Lfailure
121+
fmov s1, #-1.0
122+
fmov s2, wzr
123+
fdiv s1, s1, s2
124+
fcmp s0, s1
125+
blo .Lfailure
126+
fcmpe s0, s1
127+
blo .Lfailure
128+
129+
fmov d0, #1.0
130+
fmov d1, xzr
131+
fdiv d0, d0, d1
132+
fcmp d0, d0
133+
bne .Lfailure
134+
fcmpe d0, d0
135+
bne .Lfailure
136+
fmov d1, #-1.0
137+
fmov d2, xzr
138+
fdiv d1, d1, d2
139+
fcmp d0, d1
140+
blo .Lfailure
141+
fcmpe d0, d1
142+
blo .Lfailure
143+
144+
pass
145+
.Lfailure:
146+
fail

0 commit comments

Comments
 (0)