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interp.c
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2493 lines (2170 loc) · 69.1 KB
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/*> interp.c <*/
/* Simulator for the MIPS architecture.
This file is part of the MIPS sim
THIS SOFTWARE IS NOT COPYRIGHTED
Cygnus offers the following for use in the public domain. Cygnus
makes no warranty with regard to the software or it's performance
and the user accepts the software "AS IS" with all faults.
CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
NOTEs:
The IDT monitor (found on the VR4300 board), seems to lie about
register contents. It seems to treat the registers as sign-extended
32-bit values. This cause *REAL* problems when single-stepping 64-bit
code on the hardware.
*/
#include "config.h"
#include "bfd.h"
#include "sim-main.h"
#include "sim-utils.h"
#include "sim-options.h"
#include "sim-assert.h"
#include "sim-hw.h"
#include "itable.h"
#include "config.h"
#include <stdio.h>
#include <stdarg.h>
#include <ansidecl.h>
#include <ctype.h>
#include <limits.h>
#include <math.h>
#ifdef HAVE_STDLIB_H
#include <stdlib.h>
#endif
#ifdef HAVE_STRING_H
#include <string.h>
#else
#ifdef HAVE_STRINGS_H
#include <strings.h>
#endif
#endif
#include "getopt.h"
#include "libiberty.h"
#include "bfd.h"
#include "elf-bfd.h"
#include "gdb/callback.h" /* GDB simulator callback interface */
#include "gdb/remote-sim.h" /* GDB simulator interface */
char* pr_addr (SIM_ADDR addr);
char* pr_uword64 (uword64 addr);
/* Within interp.c we refer to the sim_state and sim_cpu directly. */
#define CPU cpu
#define SD sd
/* The following reserved instruction value is used when a simulator
trap is required. NOTE: Care must be taken, since this value may be
used in later revisions of the MIPS ISA. */
#define RSVD_INSTRUCTION (0x00000039)
#define RSVD_INSTRUCTION_MASK (0xFC00003F)
#define RSVD_INSTRUCTION_ARG_SHIFT 6
#define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
/* Bits in the Debug register */
#define Debug_DBD 0x80000000 /* Debug Branch Delay */
#define Debug_DM 0x40000000 /* Debug Mode */
#define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
/*---------------------------------------------------------------------------*/
/*-- GDB simulator interface ------------------------------------------------*/
/*---------------------------------------------------------------------------*/
static void ColdReset (SIM_DESC sd);
/*---------------------------------------------------------------------------*/
#define DELAYSLOT() {\
if (STATE & simDELAYSLOT)\
sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
STATE |= simDELAYSLOT;\
}
#define JALDELAYSLOT() {\
DELAYSLOT ();\
STATE |= simJALDELAYSLOT;\
}
#define NULLIFY() {\
STATE &= ~simDELAYSLOT;\
STATE |= simSKIPNEXT;\
}
#define CANCELDELAYSLOT() {\
DSSTATE = 0;\
STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
}
#define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
#define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
/* Note that the monitor code essentially assumes this layout of memory.
If you change these, change the monitor code, too. */
/* FIXME Currently addresses are truncated to 32-bits, see
mips/sim-main.c:address_translation(). If that changes, then these
values will need to be extended, and tested for more carefully. */
#define K0BASE (0x80000000)
#define K0SIZE (0x20000000)
#define K1BASE (0xA0000000)
#define K1SIZE (0x20000000)
/* Simple run-time monitor support.
We emulate the monitor by placing magic reserved instructions at
the monitor's entry points; when we hit these instructions, instead
of raising an exception (as we would normally), we look at the
instruction and perform the appropriate monitory operation.
`*_monitor_base' are the physical addresses at which the corresponding
monitor vectors are located. `0' means none. By default,
install all three.
The RSVD_INSTRUCTION... macros specify the magic instructions we
use at the monitor entry points. */
static int firmware_option_p = 0;
static SIM_ADDR idt_monitor_base = 0xBFC00000;
static SIM_ADDR pmon_monitor_base = 0xBFC00500;
static SIM_ADDR lsipmon_monitor_base = 0xBFC00200;
static SIM_RC sim_firmware_command (SIM_DESC sd, char* arg);
#define MEM_SIZE (8 << 20) /* 8 MBytes */
#if WITH_TRACE_ANY_P
static char *tracefile = "trace.din"; /* default filename for trace log */
FILE *tracefh = NULL;
static void open_trace (SIM_DESC sd);
#else
#define open_trace(sd)
#endif
static const char * get_insn_name (sim_cpu *, int);
/* simulation target board. NULL=canonical */
static char* board = NULL;
static DECLARE_OPTION_HANDLER (mips_option_handler);
enum {
OPTION_DINERO_TRACE = OPTION_START,
OPTION_DINERO_FILE,
OPTION_FIRMWARE,
OPTION_INFO_MEMORY,
OPTION_BOARD
};
static int display_mem_info = 0;
static SIM_RC
mips_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt, char *arg,
int is_command)
{
int cpu_nr;
switch (opt)
{
case OPTION_DINERO_TRACE: /* ??? */
#if WITH_TRACE_ANY_P
/* Eventually the simTRACE flag could be treated as a toggle, to
allow external control of the program points being traced
(i.e. only from main onwards, excluding the run-time setup,
etc.). */
for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
{
sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
if (arg == NULL)
STATE |= simTRACE;
else if (strcmp (arg, "yes") == 0)
STATE |= simTRACE;
else if (strcmp (arg, "no") == 0)
STATE &= ~simTRACE;
else if (strcmp (arg, "on") == 0)
STATE |= simTRACE;
else if (strcmp (arg, "off") == 0)
STATE &= ~simTRACE;
else
{
fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
return SIM_RC_FAIL;
}
}
return SIM_RC_OK;
#else /* !WITH_TRACE_ANY_P */
fprintf(stderr,"\
Simulator constructed without dinero tracing support (for performance).\n\
Re-compile simulator with \"-DWITH_TRACE_ANY_P\" to enable this option.\n");
return SIM_RC_FAIL;
#endif /* !WITH_TRACE_ANY_P */
case OPTION_DINERO_FILE:
#if WITH_TRACE_ANY_P
if (optarg != NULL) {
char *tmp;
tmp = (char *)malloc(strlen(optarg) + 1);
if (tmp == NULL)
{
sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
return SIM_RC_FAIL;
}
else {
strcpy(tmp,optarg);
tracefile = tmp;
sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
}
}
#endif /* WITH_TRACE_ANY_P */
return SIM_RC_OK;
case OPTION_FIRMWARE:
return sim_firmware_command (sd, arg);
case OPTION_BOARD:
{
if (arg)
{
board = zalloc(strlen(arg) + 1);
strcpy(board, arg);
}
return SIM_RC_OK;
}
case OPTION_INFO_MEMORY:
display_mem_info = 1;
break;
}
return SIM_RC_OK;
}
static const OPTION mips_options[] =
{
{ {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
'\0', "on|off", "Enable dinero tracing",
mips_option_handler },
{ {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
'\0', "FILE", "Write dinero trace to FILE",
mips_option_handler },
{ {"firmware", required_argument, NULL, OPTION_FIRMWARE},
'\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor",
mips_option_handler },
{ {"board", required_argument, NULL, OPTION_BOARD},
'\0', "none" /* rely on compile-time string concatenation for other options */
#define BOARD_JMR3904 "jmr3904"
"|" BOARD_JMR3904
#define BOARD_JMR3904_PAL "jmr3904pal"
"|" BOARD_JMR3904_PAL
#define BOARD_JMR3904_DEBUG "jmr3904debug"
"|" BOARD_JMR3904_DEBUG
#define BOARD_BSP "bsp"
"|" BOARD_BSP
, "Customize simulation for a particular board.", mips_option_handler },
/* These next two options have the same names as ones found in the
memory_options[] array in common/sim-memopt.c. This is because
the intention is to provide an alternative handler for those two
options. We need an alternative handler because the memory
regions are not set up until after the command line arguments
have been parsed, and so we cannot display the memory info whilst
processing the command line. There is a hack in sim_open to
remove these handlers when we want the real --memory-info option
to work. */
{ { "info-memory", no_argument, NULL, OPTION_INFO_MEMORY },
'\0', NULL, "List configured memory regions", mips_option_handler },
{ { "memory-info", no_argument, NULL, OPTION_INFO_MEMORY },
'\0', NULL, NULL, mips_option_handler },
{ {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
};
int interrupt_pending;
void
interrupt_event (SIM_DESC sd, void *data)
{
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
address_word cia = CPU_PC_GET (cpu);
if (SR & status_IE)
{
interrupt_pending = 0;
SignalExceptionInterrupt (1); /* interrupt "1" */
}
else if (!interrupt_pending)
sim_events_schedule (sd, 1, interrupt_event, data);
}
/*---------------------------------------------------------------------------*/
/*-- Device registration hook -----------------------------------------------*/
/*---------------------------------------------------------------------------*/
static void device_init(SIM_DESC sd) {
#ifdef DEVICE_INIT
extern void register_devices(SIM_DESC);
register_devices(sd);
#endif
}
/*---------------------------------------------------------------------------*/
/*-- GDB simulator interface ------------------------------------------------*/
/*---------------------------------------------------------------------------*/
static sim_cia
mips_pc_get (sim_cpu *cpu)
{
return PC;
}
static void
mips_pc_set (sim_cpu *cpu, sim_cia pc)
{
PC = pc;
}
static int mips_reg_fetch (SIM_CPU *, int, unsigned char *, int);
static int mips_reg_store (SIM_CPU *, int, unsigned char *, int);
SIM_DESC
sim_open (SIM_OPEN_KIND kind, host_callback *cb,
struct bfd *abfd, char * const *argv)
{
int i;
SIM_DESC sd = sim_state_alloc (kind, cb);
sim_cpu *cpu;
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
/* The cpu data is kept in a separately allocated chunk of memory. */
if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
return 0;
cpu = STATE_CPU (sd, 0); /* FIXME */
/* FIXME: watchpoints code shouldn't need this */
STATE_WATCHPOINTS (sd)->pc = &(PC);
STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
/* Initialize the mechanism for doing insn profiling. */
CPU_INSN_NAME (cpu) = get_insn_name;
CPU_MAX_INSNS (cpu) = nr_itable_entries;
STATE = 0;
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
return 0;
sim_add_option_table (sd, NULL, mips_options);
/* The parser will print an error message for us, so we silently return. */
if (sim_parse_args (sd, argv) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
sim_module_uninstall (sd);
return 0;
}
/* handle board-specific memory maps */
if (board == NULL)
{
/* Allocate core managed memory */
sim_memopt *entry, *match = NULL;
address_word mem_size = 0;
int mapped = 0;
/* For compatibility with the old code - under this (at level one)
are the kernel spaces K0 & K1. Both of these map to a single
smaller sub region */
sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
/* Look for largest memory region defined on command-line at
phys address 0. */
for (entry = STATE_MEMOPT (sd); entry != NULL; entry = entry->next)
{
/* If we find an entry at address 0, then we will end up
allocating a new buffer in the "memory alias" command
below. The region at address 0 will be deleted. */
address_word size = (entry->modulo != 0
? entry->modulo : entry->nr_bytes);
if (entry->addr == 0
&& (!match || entry->level < match->level))
match = entry;
else if (entry->addr == K0BASE || entry->addr == K1BASE)
mapped = 1;
else
{
sim_memopt *alias;
for (alias = entry->alias; alias != NULL; alias = alias->next)
{
if (alias->addr == 0
&& (!match || entry->level < match->level))
match = entry;
else if (alias->addr == K0BASE || alias->addr == K1BASE)
mapped = 1;
}
}
}
if (!mapped)
{
if (match)
{
/* Get existing memory region size. */
mem_size = (match->modulo != 0
? match->modulo : match->nr_bytes);
/* Delete old region. */
sim_do_commandf (sd, "memory delete %d:0x%lx@%d",
match->space, match->addr, match->level);
}
else if (mem_size == 0)
mem_size = MEM_SIZE;
/* Limit to KSEG1 size (512MB) */
if (mem_size > K1SIZE)
mem_size = K1SIZE;
/* memory alias K1BASE@1,K1SIZE%MEMSIZE,K0BASE */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
K1BASE, K1SIZE, (long)mem_size, K0BASE);
}
device_init(sd);
}
else if (board != NULL
&& (strcmp(board, BOARD_BSP) == 0))
{
int i;
STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
/* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
0x9FC00000,
4 * 1024 * 1024, /* 4 MB */
0xBFC00000);
/* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
0x80000000,
4 * 1024 * 1024, /* 4 MB */
0xA0000000);
/* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
for (i=0; i<8; i++) /* 32 MB total */
{
unsigned size = 4 * 1024 * 1024; /* 4 MB */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
0x88000000 + (i * size),
size,
0xA8000000 + (i * size));
}
}
#if (WITH_HW)
else if (board != NULL
&& (strcmp(board, BOARD_JMR3904) == 0 ||
strcmp(board, BOARD_JMR3904_PAL) == 0 ||
strcmp(board, BOARD_JMR3904_DEBUG) == 0))
{
/* match VIRTUAL memory layout of JMR-TX3904 board */
int i;
/* --- disable monitor unless forced on by user --- */
if (! firmware_option_p)
{
idt_monitor_base = 0;
pmon_monitor_base = 0;
lsipmon_monitor_base = 0;
}
/* --- environment --- */
STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
/* --- memory --- */
/* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
0x9FC00000,
4 * 1024 * 1024, /* 4 MB */
0xBFC00000);
/* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
0x80000000,
4 * 1024 * 1024, /* 4 MB */
0xA0000000);
/* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
for (i=0; i<8; i++) /* 32 MB total */
{
unsigned size = 4 * 1024 * 1024; /* 4 MB */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
0x88000000 + (i * size),
size,
0xA8000000 + (i * size));
}
/* Dummy memory regions for unsimulated devices - sorted by address */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2500000, 0x004); /* LED/switch */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x900); /* DRAMC */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFE000, 0x01c); /* EBIF */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
/* --- simulated devices --- */
sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
sim_hw_parse (sd, "/tx3904cpu");
sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
sim_hw_parse (sd, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
{
/* FIXME: poking at dv-sockser internals, use tcp backend if
--sockser_addr option was given.*/
extern char* sockser_addr;
if(sockser_addr == NULL)
sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend stdio");
else
sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend tcp");
}
sim_hw_parse (sd, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
sim_hw_parse (sd, "/tx3904sio@0xfffff400/backend stdio");
/* -- device connections --- */
sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
sim_hw_parse (sd, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
sim_hw_parse (sd, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
/* add PAL timer & I/O module */
if(! strcmp(board, BOARD_JMR3904_PAL))
{
/* the device */
sim_hw_parse (sd, "/pal@0xffff0000");
sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
/* wire up interrupt ports to irc */
sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
}
if(! strcmp(board, BOARD_JMR3904_DEBUG))
{
/* -- DEBUG: glue interrupt generators --- */
sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
}
device_init(sd);
}
#endif
if (display_mem_info)
{
struct option_list * ol;
struct option_list * prev;
/* This is a hack. We want to execute the real --memory-info command
line switch which is handled in common/sim-memopts.c, not the
override we have defined in this file. So we remove the
mips_options array from the state options list. This is safe
because we have now processed all of the command line. */
for (ol = STATE_OPTIONS (sd), prev = NULL;
ol != NULL;
prev = ol, ol = ol->next)
if (ol->options == mips_options)
break;
SIM_ASSERT (ol != NULL);
if (prev == NULL)
STATE_OPTIONS (sd) = ol->next;
else
prev->next = ol->next;
sim_do_commandf (sd, "memory-info");
}
/* check for/establish the a reference program image */
if (sim_analyze_program (sd,
(STATE_PROG_ARGV (sd) != NULL
? *STATE_PROG_ARGV (sd)
: NULL),
abfd) != SIM_RC_OK)
{
sim_module_uninstall (sd);
return 0;
}
/* Configure/verify the target byte order and other runtime
configuration options */
if (sim_config (sd) != SIM_RC_OK)
{
sim_module_uninstall (sd);
return 0;
}
if (sim_post_argv_init (sd) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
sim_module_uninstall (sd);
return 0;
}
/* verify assumptions the simulator made about the host type system.
This macro does not return if there is a problem */
SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
/* This is NASTY, in that we are assuming the size of specific
registers: */
{
int rn;
for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
{
if (rn < 32)
cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
else if ((rn >= FGR_BASE) && (rn < (FGR_BASE + NR_FGR)))
cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
else if ((rn >= 33) && (rn <= 37))
cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
else if ((rn == SRIDX)
|| (rn == FCR0IDX)
|| (rn == FCR31IDX)
|| ((rn >= 72) && (rn <= 89)))
cpu->register_widths[rn] = 32;
else
cpu->register_widths[rn] = 0;
}
}
if (STATE & simTRACE)
open_trace(sd);
/*
sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
idt_monitor_base,
pmon_monitor_base,
lsipmon_monitor_base);
*/
/* Write the monitor trap address handlers into the monitor (eeprom)
address space. This can only be done once the target endianness
has been determined. */
if (idt_monitor_base != 0)
{
unsigned loop;
unsigned idt_monitor_size = 1 << 11;
/* the default monitor region */
sim_do_commandf (sd, "memory region 0x%x,0x%x",
idt_monitor_base, idt_monitor_size);
/* Entry into the IDT monitor is via fixed address vectors, and
not using machine instructions. To avoid clashing with use of
the MIPS TRAP system, we place our own (simulator specific)
"undefined" instructions into the relevant vector slots. */
for (loop = 0; (loop < idt_monitor_size); loop += 4)
{
address_word vaddr = (idt_monitor_base + loop);
unsigned32 insn = (RSVD_INSTRUCTION |
(((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK)
<< RSVD_INSTRUCTION_ARG_SHIFT));
H2T (insn);
sim_write (sd, vaddr, (unsigned char *)&insn, sizeof (insn));
}
}
if ((pmon_monitor_base != 0) || (lsipmon_monitor_base != 0))
{
/* The PMON monitor uses the same address space, but rather than
branching into it the address of a routine is loaded. We can
cheat for the moment, and direct the PMON routine to IDT style
instructions within the monitor space. This relies on the IDT
monitor not using the locations from 0xBFC00500 onwards as its
entry points.*/
unsigned loop;
for (loop = 0; (loop < 24); loop++)
{
unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
switch (loop)
{
case 0: /* read */
value = 7;
break;
case 1: /* write */
value = 8;
break;
case 2: /* open */
value = 6;
break;
case 3: /* close */
value = 10;
break;
case 5: /* printf */
value = ((0x500 - 16) / 8); /* not an IDT reason code */
break;
case 8: /* cliexit */
value = 17;
break;
case 11: /* flush_cache */
value = 28;
break;
}
SIM_ASSERT (idt_monitor_base != 0);
value = ((unsigned int) idt_monitor_base + (value * 8));
H2T (value);
if (pmon_monitor_base != 0)
{
address_word vaddr = (pmon_monitor_base + (loop * 4));
sim_write (sd, vaddr, (unsigned char *)&value, sizeof (value));
}
if (lsipmon_monitor_base != 0)
{
address_word vaddr = (lsipmon_monitor_base + (loop * 4));
sim_write (sd, vaddr, (unsigned char *)&value, sizeof (value));
}
}
/* Write an abort sequence into the TRAP (common) exception vector
addresses. This is to catch code executing a TRAP (et.al.)
instruction without installing a trap handler. */
if ((idt_monitor_base != 0) ||
(pmon_monitor_base != 0) ||
(lsipmon_monitor_base != 0))
{
unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
HALT_INSTRUCTION /* BREAK */ };
H2T (halt[0]);
H2T (halt[1]);
sim_write (sd, 0x80000000, (unsigned char *) halt, sizeof (halt));
sim_write (sd, 0x80000180, (unsigned char *) halt, sizeof (halt));
sim_write (sd, 0x80000200, (unsigned char *) halt, sizeof (halt));
/* XXX: Write here unconditionally? */
sim_write (sd, 0xBFC00200, (unsigned char *) halt, sizeof (halt));
sim_write (sd, 0xBFC00380, (unsigned char *) halt, sizeof (halt));
sim_write (sd, 0xBFC00400, (unsigned char *) halt, sizeof (halt));
}
}
/* CPU specific initialization. */
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
{
SIM_CPU *cpu = STATE_CPU (sd, i);
CPU_REG_FETCH (cpu) = mips_reg_fetch;
CPU_REG_STORE (cpu) = mips_reg_store;
CPU_PC_FETCH (cpu) = mips_pc_get;
CPU_PC_STORE (cpu) = mips_pc_set;
}
return sd;
}
#if WITH_TRACE_ANY_P
static void
open_trace (SIM_DESC sd)
{
tracefh = fopen(tracefile,"wb+");
if (tracefh == NULL)
{
sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
tracefh = stderr;
}
}
#endif
/* Return name of an insn, used by insn profiling. */
static const char *
get_insn_name (sim_cpu *cpu, int i)
{
return itable[i].name;
}
void
mips_sim_close (SIM_DESC sd, int quitting)
{
#if WITH_TRACE_ANY_P
if (tracefh != NULL && tracefh != stderr)
fclose(tracefh);
tracefh = NULL;
#endif
}
static int
mips_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
/* NOTE: gdb (the client) stores registers in target byte order
while the simulator uses host byte order */
/* Unfortunately this suffers from the same problem as the register
numbering one. We need to know what the width of each logical
register number is for the architecture being simulated. */
if (cpu->register_widths[rn] == 0)
{
sim_io_eprintf (CPU_STATE (cpu), "Invalid register width for %d (register store ignored)\n", rn);
return 0;
}
if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
{
cpu->fpr_state[rn - FGR_BASE] = fmt_uninterpreted;
if (cpu->register_widths[rn] == 32)
{
if (length == 8)
{
cpu->fgr[rn - FGR_BASE] =
(unsigned32) T2H_8 (*(unsigned64*)memory);
return 8;
}
else
{
cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
return 4;
}
}
else
{
if (length == 8)
{
cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory);
return 8;
}
else
{
cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
return 4;
}
}
}
if (cpu->register_widths[rn] == 32)
{
if (length == 8)
{
cpu->registers[rn] =
(unsigned32) T2H_8 (*(unsigned64*)memory);
return 8;
}
else
{
cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
return 4;
}
}
else
{
if (length == 8)
{
cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
return 8;
}
else
{
cpu->registers[rn] = (signed32) T2H_4(*(unsigned32*)memory);
return 4;
}
}
return 0;
}
static int
mips_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
/* NOTE: gdb (the client) stores registers in target byte order
while the simulator uses host byte order */
if (cpu->register_widths[rn] == 0)
{
sim_io_eprintf (CPU_STATE (cpu), "Invalid register width for %d (register fetch ignored)\n", rn);
return 0;
}
/* Any floating point register */
if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
{
if (cpu->register_widths[rn] == 32)
{
if (length == 8)
{
*(unsigned64*)memory =
H2T_8 ((unsigned32) (cpu->fgr[rn - FGR_BASE]));
return 8;
}
else
{
*(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]);
return 4;
}
}
else
{
if (length == 8)
{
*(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]);
return 8;
}
else
{
*(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->fgr[rn - FGR_BASE]));
return 4;
}
}
}
if (cpu->register_widths[rn] == 32)
{
if (length == 8)
{
*(unsigned64*)memory =
H2T_8 ((unsigned32) (cpu->registers[rn]));
return 8;
}
else
{
*(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
return 4;
}
}
else
{
if (length == 8)
{
*(unsigned64*)memory =
H2T_8 ((unsigned64) (cpu->registers[rn]));
return 8;
}
else
{
*(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
return 4;
}
}
return 0;