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6528 lines (5755 loc) · 120 KB
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// -*- C -*-
//
// <insn> ::=
// <insn-word> { "+" <insn-word> }
// ":" <format-name>
// ":" <filter-flags>
// ":" <options>
// ":" <name>
// <nl>
// { <insn-model> }
// { <insn-mnemonic> }
// <code-block>
//
// IGEN config - mips16
// :option:16::insn-bit-size:16
// :option:16::hi-bit-nr:15
:option:16::insn-specifying-widths:true
:option:16::gen-delayed-branch:false
// IGEN config - mips32/64..
// :option:32::insn-bit-size:32
// :option:32::hi-bit-nr:31
:option:32::insn-specifying-widths:true
:option:32::gen-delayed-branch:false
// Generate separate simulators for each target
// :option:::multi-sim:true
// Models known by this simulator are defined below.
//
// When placing models in the instruction descriptions, please place
// them one per line, in the order given here.
// MIPS ISAs:
//
// Instructions and related functions for these models are included in
// this file.
:model:::mipsI:mips3000:
:model:::mipsII:mips6000:
:model:::mipsIII:mips4000:
:model:::mipsIV:mips8000:
:model:::mipsV:mipsisaV:
:model:::mips32:mipsisa32:
:model:::mips32r2:mipsisa32r2:
:model:::mips64:mipsisa64:
:model:::mips64r2:mipsisa64r2:
// Vendor ISAs:
//
// Standard MIPS ISA instructions used for these models are listed here,
// as are functions needed by those standard instructions. Instructions
// which are model-dependent and which are not in the standard MIPS ISAs
// (or which pre-date or use different encodings than the standard
// instructions) are (for the most part) in separate .igen files.
:model:::vr4100:mips4100: // vr.igen
:model:::vr4120:mips4120:
:model:::vr5000:mips5000:
:model:::vr5400:mips5400:
:model:::vr5500:mips5500:
:model:::r3900:mips3900: // tx.igen
// MIPS Application Specific Extensions (ASEs)
//
// Instructions for the ASEs are in separate .igen files.
// ASEs add instructions on to a base ISA.
:model:::mips16:mips16: // m16.igen (and m16.dc)
:model:::mips16e:mips16e: // m16e.igen
:model:::mips3d:mips3d: // mips3d.igen
:model:::mdmx:mdmx: // mdmx.igen
:model:::dsp:dsp: // dsp.igen
:model:::dsp2:dsp2: // dsp2.igen
:model:::smartmips:smartmips: // smartmips.igen
:model:::micromips32:micromips64: // micromips.igen
:model:::micromips64:micromips64: // micromips.igen
:model:::micromipsdsp:micromipsdsp: // micromipsdsp.igen
// Vendor Extensions
//
// Instructions specific to these extensions are in separate .igen files.
// Extensions add instructions on to a base ISA.
:model:::sb1:sb1: // sb1.igen
// Pseudo instructions known by IGEN
:internal::::illegal:
{
SignalException (ReservedInstruction, 0);
}
// Pseudo instructions known by interp.c
// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
000000,5.*,5.*,5.*,5.OP,111001:SPECIAL:32::RSVD
"rsvd <OP>"
{
SignalException (ReservedInstruction, instruction_0);
}
// Helper:
//
// Simulate a 32 bit delayslot instruction
//
:function:::address_word:delayslot32:address_word target
{
instruction_word delay_insn;
sim_events_slip (SD, 1);
DSPC = CIA;
CIA = CIA + 4; /* NOTE not mips16 */
STATE |= simDELAYSLOT;
delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
ENGINE_ISSUE_PREFIX_HOOK();
idecode_issue (CPU_, delay_insn, (CIA));
STATE &= ~simDELAYSLOT;
return target;
}
:function:::address_word:nullify_next_insn32:
{
sim_events_slip (SD, 1);
dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
return CIA + 8;
}
// Helper:
//
// Calculate an effective address given a base and an offset.
//
:function:::address_word:loadstore_ea:address_word base, address_word offset
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*vr4100:
*vr5000:
*r3900:
*micromips32:
{
return base + offset;
}
:function:::address_word:loadstore_ea:address_word base, address_word offset
*mips64:
*mips64r2:
*micromips64:
{
#if 0 /* XXX FIXME: enable this only after some additional testing. */
/* If in user mode and UX is not set, use 32-bit compatibility effective
address computations as defined in the MIPS64 Architecture for
Programmers Volume III, Revision 0.95, section 4.9. */
if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
== (ksu_user << status_KSU_shift))
return (address_word)((signed32)base + (signed32)offset);
#endif
return base + offset;
}
// Helper:
//
// Check that a 32-bit register value is properly sign-extended.
// (See NotWordValue in ISA spec.)
//
:function:::int:not_word_value:unsigned_word value
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*vr4100:
*vr5000:
*r3900:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*micromips32:
*micromips64:
{
#if WITH_TARGET_WORD_BITSIZE == 64
return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
#else
return 0;
#endif
}
// Helper:
//
// Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
// theoretically portable code which invokes non-portable behaviour from
// running with no indication of the portability issue.
// (See definition of UNPREDICTABLE in ISA spec.)
//
:function:::void:unpredictable:
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*vr4100:
*vr5000:
*r3900:
{
}
:function:::void:unpredictable:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*micromips32:
*micromips64:
{
unpredictable_action (CPU, CIA);
}
// Helpers:
//
// Check that an access to a HI/LO register meets timing requirements
//
// In all MIPS ISAs,
//
// OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
// makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
//
// The following restrictions exist for MIPS I - MIPS III:
//
// MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
// in between makes MF UNPREDICTABLE. (2)
//
// MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
// in between makes MF UNPREDICTABLE. (3)
//
// On the r3900, restriction (2) is not present, and restriction (3) is not
// present for multiplication.
//
// Unfortunately, there seems to be some confusion about whether the last
// two restrictions should apply to "MIPS IV" as well. One edition of
// the MIPS IV ISA says they do, but references in later ISA documents
// suggest they don't.
//
// In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
// these restrictions, while others, like the VR5500, don't. To accomodate
// such differences, the MIPS IV and MIPS V version of these helper functions
// use auxillary routines to determine whether the restriction applies.
// check_mf_cycles:
//
// Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
// to check for restrictions (2) and (3) above.
//
:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
{
if (history->mf.timestamp + 3 > time)
{
sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
itable[MY_INDEX].name,
new, (long) CIA,
(long) history->mf.cia);
return 0;
}
return 1;
}
// check_mt_hilo:
//
// Check for restriction (2) above (for ISAs/processors that have it),
// and record timestamps for restriction (1) above.
//
:function:::int:check_mt_hilo:hilo_history *history
*mipsI:
*mipsII:
*mipsIII:
*vr4100:
*vr5000:
{
signed64 time = sim_events_time (SD);
int ok = check_mf_cycles (SD_, history, time, "MT");
history->mt.timestamp = time;
history->mt.cia = CIA;
return ok;
}
:function:::int:check_mt_hilo:hilo_history *history
*mipsIV:
*mipsV:
{
signed64 time = sim_events_time (SD);
int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
|| check_mf_cycles (SD_, history, time, "MT"));
history->mt.timestamp = time;
history->mt.cia = CIA;
return ok;
}
:function:::int:check_mt_hilo:hilo_history *history
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*r3900:
*micromips32:
*micromips64:
{
signed64 time = sim_events_time (SD);
history->mt.timestamp = time;
history->mt.cia = CIA;
return 1;
}
// check_mf_hilo:
//
// Check for restriction (1) above, and record timestamps for
// restriction (2) and (3) above.
//
:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*vr4100:
*vr5000:
*r3900:
*micromips32:
*micromips64:
{
signed64 time = sim_events_time (SD);
int ok = 1;
if (peer != NULL
&& peer->mt.timestamp > history->op.timestamp
&& history->mt.timestamp < history->op.timestamp
&& ! (history->mf.timestamp > history->op.timestamp
&& history->mf.timestamp < peer->mt.timestamp)
&& ! (peer->mf.timestamp > history->op.timestamp
&& peer->mf.timestamp < peer->mt.timestamp))
{
/* The peer has been written to since the last OP yet we have
not */
sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
itable[MY_INDEX].name,
(long) CIA,
(long) history->op.cia,
(long) peer->mt.cia);
ok = 0;
}
history->mf.timestamp = time;
history->mf.cia = CIA;
return ok;
}
// check_mult_hilo:
//
// Check for restriction (3) above (for ISAs/processors that have it)
// for MULT ops, and record timestamps for restriction (1) above.
//
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
*mipsI:
*mipsII:
*mipsIII:
*vr4100:
*vr5000:
{
signed64 time = sim_events_time (SD);
int ok = (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP"));
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
lo->op.cia = CIA;
return ok;
}
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
*mipsIV:
*mipsV:
{
signed64 time = sim_events_time (SD);
int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
|| (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP")));
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
lo->op.cia = CIA;
return ok;
}
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*r3900:
*micromips32:
*micromips64:
{
/* FIXME: could record the fact that a stall occured if we want */
signed64 time = sim_events_time (SD);
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
lo->op.cia = CIA;
return 1;
}
// check_div_hilo:
//
// Check for restriction (3) above (for ISAs/processors that have it)
// for DIV ops, and record timestamps for restriction (1) above.
//
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
*mipsI:
*mipsII:
*mipsIII:
*vr4100:
*vr5000:
*r3900:
{
signed64 time = sim_events_time (SD);
int ok = (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP"));
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
lo->op.cia = CIA;
return ok;
}
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
*mipsIV:
*mipsV:
{
signed64 time = sim_events_time (SD);
int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
|| (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP")));
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
lo->op.cia = CIA;
return ok;
}
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
*mips32:
*mips32r2:
*mips64:
*mips64r2:
*micromips32:
*micromips64:
{
signed64 time = sim_events_time (SD);
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
lo->op.cia = CIA;
return 1;
}
// Helper:
//
// Check that the 64-bit instruction can currently be used, and signal
// a ReservedInstruction exception if not.
//
:function:::void:check_u64:instruction_word insn
*mipsIII:
*mipsIV:
*mipsV:
*vr4100:
*vr5000:
*vr5400:
*vr5500:
{
// The check should be similar to mips64 for any with PX/UX bit equivalents.
}
:function:::void:check_u64:instruction_word insn
*mips16e:
*mips64:
*mips64r2:
*mips32:
*mips32r2:
*micromips64:
*micromips32:
{
#if 0 /* XXX FIXME: enable this only after some additional testing. */
if (UserMode && (SR & (status_UX|status_PX)) == 0)
SignalException (ReservedInstruction, insn);
#endif
}
//
// MIPS Architecture:
//
// CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
//
:function:::void:do_add:int rs, int rt, int rd
{
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
ALU32_BEGIN (GPR[rs]);
ALU32_ADD (GPR[rt]);
ALU32_END (GPR[rd]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[rd]);
}
:function:::void:do_addi:int rs, int rt, unsigned16 immediate
{
if (NotWordValue (GPR[rs]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
{
ALU32_BEGIN (GPR[rs]);
ALU32_ADD (EXTEND16 (immediate));
ALU32_END (GPR[rt]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[rt]);
}
:function:::void:do_andi:int rs, int rt, unsigned int immediate
{
TRACE_ALU_INPUT2 (GPR[rs], immediate);
GPR[rt] = GPR[rs] & immediate;
TRACE_ALU_RESULT (GPR[rt]);
}
:function:::void:do_dadd:int rd, int rs, int rt
{
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
ALU64_BEGIN (GPR[rs]);
ALU64_ADD (GPR[rt]);
ALU64_END (GPR[rd]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[rd]);
}
:function:::void:do_daddi:int rt, int rs, int immediate
{
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
{
ALU64_BEGIN (GPR[rs]);
ALU64_ADD (EXTEND16 (immediate));
ALU64_END (GPR[rt]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[rt]);
}
:function:::void:do_dsll32:int rd, int rt, int shift
{
int s = 32 + shift;
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = GPR[rt] << s;
TRACE_ALU_RESULT (GPR[rd]);
}
:function:::void:do_dsra32:int rd, int rt, int shift
{
int s = 32 + shift;
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = ((signed64) GPR[rt]) >> s;
TRACE_ALU_RESULT (GPR[rd]);
}
:function:::void:do_dsrl32:int rd, int rt, int shift
{
int s = 32 + shift;
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = (unsigned64) GPR[rt] >> s;
TRACE_ALU_RESULT (GPR[rd]);
}
:function:::void:do_dsub:int rd, int rs, int rt
{
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
ALU64_BEGIN (GPR[rs]);
ALU64_SUB (GPR[rt]);
ALU64_END (GPR[rd]); /* This checks for overflow. */
}
TRACE_ALU_RESULT (GPR[rd]);
}
:function:::void:do_break:address_word instruction_0
{
/* Check for some break instruction which are reserved for use by the
simulator. */
unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
{
sim_engine_halt (SD, CPU, NULL, cia,
sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
}
else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
{
if (STATE & simDELAYSLOT)
PC = cia - 4; /* reference the branch instruction */
else
PC = cia;
SignalException (BreakPoint, instruction_0);
}
else
{
/* If we get this far, we're not an instruction reserved by the sim. Raise
the exception. */
SignalException (BreakPoint, instruction_0);
}
}
:function:::void:do_break16:address_word instruction_0
{
if (STATE & simDELAYSLOT)
PC = cia - 2; /* reference the branch instruction */
else
PC = cia;
SignalException (BreakPoint, instruction_0);
}
:function:::void:do_clo:int rd, int rs
{
unsigned32 temp = GPR[rs];
unsigned32 i, mask;
if (NotWordValue (GPR[rs]))
Unpredictable ();
TRACE_ALU_INPUT1 (GPR[rs]);
for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
{
if ((temp & mask) == 0)
break;
mask >>= 1;
}
GPR[rd] = EXTEND32 (i);
TRACE_ALU_RESULT (GPR[rd]);
}
:function:::void:do_clz:int rd, int rs
{
unsigned32 temp = GPR[rs];
unsigned32 i, mask;
if (NotWordValue (GPR[rs]))
Unpredictable ();
TRACE_ALU_INPUT1 (GPR[rs]);
for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
{
if ((temp & mask) != 0)
break;
mask >>= 1;
}
GPR[rd] = EXTEND32 (i);
TRACE_ALU_RESULT (GPR[rd]);
}
:function:::void:do_dclo:int rd, int rs
{
unsigned64 temp = GPR[rs];
unsigned32 i;
unsigned64 mask;
TRACE_ALU_INPUT1 (GPR[rs]);
for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
{
if ((temp & mask) == 0)
break;
mask >>= 1;
}
GPR[rd] = EXTEND32 (i);
TRACE_ALU_RESULT (GPR[rd]);
}
:function:::void:do_dclz:int rd, int rs
{
unsigned64 temp = GPR[rs];
unsigned32 i;
unsigned64 mask;
TRACE_ALU_INPUT1 (GPR[rs]);
for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
{
if ((temp & mask) != 0)
break;
mask >>= 1;
}
GPR[rd] = EXTEND32 (i);
TRACE_ALU_RESULT (GPR[rd]);
}
:function:::void:do_lb:int rt, int offset, int base
{
GPR[rt] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[base],
EXTEND16 (offset)));
}
:function:::void:do_lh:int rt, int offset, int base
{
GPR[rt] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[base],
EXTEND16 (offset)));
}
:function:::void:do_lwr:int rt, int offset, int base
{
GPR[rt] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[base],
EXTEND16 (offset), GPR[rt]));
}
:function:::void:do_lwl:int rt, int offset, int base
{
GPR[rt] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[base],
EXTEND16 (offset), GPR[rt]));
}
:function:::void:do_lwc:int num, int rt, int offset, int base
{
COP_LW (num, rt, do_load (SD_, AccessLength_WORD, GPR[base],
EXTEND16 (offset)));
}
:function:::void:do_lw:int rt, int offset, int base
{
GPR[rt] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[base],
EXTEND16 (offset)));
}
:function:::void:do_lwu:int rt, int offset, int base, address_word instruction_0
{
check_u64 (SD_, instruction_0);
GPR[rt] = do_load (SD_, AccessLength_WORD, GPR[base], EXTEND16 (offset));
}
:function:::void:do_lhu:int rt, int offset, int base
{
GPR[rt] = do_load (SD_, AccessLength_HALFWORD, GPR[base], EXTEND16 (offset));
}
:function:::void:do_ldc:int num, int rt, int offset, int base
{
COP_LD (num, rt, do_load (SD_, AccessLength_DOUBLEWORD, GPR[base],
EXTEND16 (offset)));
}
:function:::void:do_lbu:int rt, int offset, int base
{
GPR[rt] = do_load (SD_, AccessLength_BYTE, GPR[base], EXTEND16 (offset));
}
:function:::void:do_ll:int rt, int insn_offset, int basereg
{
address_word base = GPR[basereg];
address_word offset = EXTEND16 (insn_offset);
{
address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr = vaddr;
if ((vaddr & 3) != 0)
{
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer,
sim_core_unaligned_signal);
}
else
{
unsigned64 memval = 0;
unsigned64 memval1 = 0;
unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
unsigned int shift = 2;
unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
unsigned int byte;
paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
LoadMemory (&memval, &memval1, AccessLength_WORD, paddr, vaddr,
isDATA, isREAL);
byte = ((vaddr & mask) ^ (bigend << shift));
GPR[rt] = EXTEND32 (memval >> (8 * byte));
LLBIT = 1;
}
}
}
:function:::void:do_lld:int rt, int roffset, int rbase
{
address_word base = GPR[rbase];
address_word offset = EXTEND16 (roffset);
{
address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr = vaddr;
if ((vaddr & 7) != 0)
{
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer,
sim_core_unaligned_signal);
}
else
{
unsigned64 memval = 0;
unsigned64 memval1 = 0;
LoadMemory (&memval, &memval1, AccessLength_DOUBLEWORD, paddr, vaddr,
isDATA, isREAL);
GPR[rt] = memval;
LLBIT = 1;
}
}
}
:function:::void:do_lui:int rt, int immediate
{
TRACE_ALU_INPUT1 (immediate);
GPR[rt] = EXTEND32 (immediate << 16);
TRACE_ALU_RESULT (GPR[rt]);
}
:function:::void:do_madd:int rs, int rt
{
signed64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
}
:function:::void:do_dsp_madd:int ac, int rs, int rt
{
signed64 temp;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
+ ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
DSPLO(ac) = EXTEND32 (temp);
DSPHI(ac) = EXTEND32 (VH4_8 (temp));
if (ac == 0)
TRACE_ALU_RESULT2 (HI, LO);
}
:function:::void:do_maddu:int rs, int rt
{
unsigned64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
}
:function:::void:do_dsp_maddu:int ac, int rs, int rt
{
unsigned64 temp;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
+ ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
if (ac == 0)
ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
DSPLO(ac) = EXTEND32 (temp);
DSPHI(ac) = EXTEND32 (VH4_8 (temp));
if (ac == 0)
TRACE_ALU_RESULT2 (HI, LO);
}
:function:::void:do_dsp_mfhi:int ac, int rd
{
if (ac == 0)
do_mfhi (SD_, rd);
else
GPR[rd] = DSPHI(ac);
}
:function:::void:do_dsp_mflo:int ac, int rd
{
if (ac == 0)
do_mflo (SD_, rd);
else
GPR[rd] = DSPLO(ac);
}
:function:::void:do_movn:int rd, int rs, int rt
{
if (GPR[rt] != 0)
{
GPR[rd] = GPR[rs];
TRACE_ALU_RESULT (GPR[rd]);
}
}
:function:::void:do_movz:int rd, int rs, int rt
{
if (GPR[rt] == 0)
{
GPR[rd] = GPR[rs];
TRACE_ALU_RESULT (GPR[rd]);
}
}
:function:::void:do_msub:int rs, int rt
{
signed64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
}
:function:::void:do_dsp_msub:int ac, int rs, int rt
{
signed64 temp;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
- ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
DSPLO(ac) = EXTEND32 (temp);
DSPHI(ac) = EXTEND32 (VH4_8 (temp));
if (ac == 0)
TRACE_ALU_RESULT2 (HI, LO);
}
:function:::void:do_msubu:int rs, int rt
{
unsigned64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
}
:function:::void:do_dsp_msubu:int ac, int rs, int rt
{
unsigned64 temp;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
- ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
DSPLO(ac) = EXTEND32 (temp);
DSPHI(ac) = EXTEND32 (VH4_8 (temp));
if (ac == 0)
TRACE_ALU_RESULT2 (HI, LO);
}
:function:::void:do_mthi:int rs
{