// Simulator definition for the micromips ASE.

// Copyright (C) 2005-2017 Free Software Foundation, Inc.

// Contributed by Imagination Technologies, Ltd.

// Written by Andrew Bennett <[email protected]>

//

// This file is part of the MIPS sim.

//

// This program is free software; you can redistribute it and/or modify

// it under the terms of the GNU General Public License as published by

// the Free Software Foundation; either version 3 of the License, or

// (at your option) any later version.

//

// This program is distributed in the hope that it will be useful,

// but WITHOUT ANY WARRANTY; without even the implied warranty of

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

// GNU General Public License for more details.

//

// You should have received a copy of the GNU General Public License

// along with this program. If not, see <http://www.gnu.org/licenses/>.

:compute:::int:TBASE:BASE:((BASE < 2) ? (16 + BASE) \: BASE)

:compute:::int:TRD:RD:((RD < 2) ? (16 + RD) \: RD)

:compute:::int:TRS:RS:((RS < 2) ? (16 + RS) \: RS)

:compute:::int:TRT:RT:((RT < 2) ? (16 + RT) \: RT)

:compute:::int:TRT_S:RT_S:((RT_S == 1 ) ? 17 \: RT_S)

:compute:::int:ERT:RT:(compute_movep_src_reg (SD_, RT))

:compute:::int:ERS:RS:(compute_movep_src_reg (SD_, RS))

:compute:::int:IMM_DEC1:IMMEDIATE:((IMMEDIATE == 7) ? -1 \: ((IMMEDIATE == 0) ? 1 \: IMMEDIATE << 2))

:compute:::int:IMM_DEC2:IMMEDIATE:((IMMEDIATE < 8) ? IMMEDIATE \: (IMMEDIATE - 16))

:compute:::int:IMM_DEC3:IMMEDIATE:((IMMEDIATE < 2) ? IMMEDIATE + 256 \: ((IMMEDIATE < 256) ? IMMEDIATE \: ((IMMEDIATE < 510) ? IMMEDIATE - 512 \: IMMEDIATE - 768)))

:compute:::int:IMM_DEC4:IMMEDIATE:(compute_andi16_imm (SD_, IMMEDIATE))

:compute:::int:IMM_DEC5:IMMEDIATE:((IMMEDIATE < 15) ? IMMEDIATE \: -1)

:compute:::int:IMM_DEC6:IMMEDIATE:((IMMEDIATE < 127) ? IMMEDIATE \: -1)

:compute:::int:SHIFT_DEC:SHIFT:((SHIFT == 0) ? 8 \: SHIFT)

:compute:::int:IMM_SHIFT_1BIT:IMMEDIATE:(IMMEDIATE << 1)

:compute:::int:IMM_SHIFT_2BIT:IMMEDIATE:(IMMEDIATE << 2)

:function:::address_word:delayslot_micromips:address_word target, address_word nia, int delayslot_instruction_size

*micromips32:

*micromips64:

*micromipsdsp:

{

instruction_word delay_insn;

sim_events_slip (SD, 1);

DSPC = CIA;

CIA = nia;

STATE |= simDELAYSLOT;

ENGINE_ISSUE_PREFIX_HOOK();

micromips_instruction_decode (SD, CPU, CIA, delayslot_instruction_size);

STATE &= ~simDELAYSLOT;

return target;

}

:function:::address_word:process_isa_mode:address_word target

*micromips32:

*micromips64:

{

SD->isa_mode = target & 0x1;

return (target & (-(1 << 1)));

}

:function:::address_word:do_micromips_jalr:int rt, int rs, address_word nia, int delayslot_instruction_size

*micromips32:

*micromips64:

{

GPR[rt] = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;

return (process_isa_mode (SD_,

delayslot_micromips (SD_, GPR[rs], nia, delayslot_instruction_size)));

}

:function:::address_word:do_micromips_jal:address_word target, address_word nia, int delayslot_instruction_size

*micromips32:

*micromips64:

{

RA = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;

return delayslot_micromips (SD_, target, nia, delayslot_instruction_size);

}

:function:::unsigned32:compute_movep_src_reg:int reg

*micromips32:

*micromips64:

{

switch(reg)

{

case 0: return 0;

case 1: return 17;

case 2: return 2;

case 3: return 3;

case 4: return 16;

case 5: return 18;

case 6: return 19;

case 7: return 20;

default: return 0;

}

}

:function:::unsigned32:compute_andi16_imm:int encoded_imm

*micromips32:

*micromips64:

{

switch (encoded_imm)

{

case 0: return 128;

case 1: return 1;

case 2: return 2;

case 3: return 3;

case 4: return 4;

case 5: return 7;

case 6: return 8;

case 7: return 15;

case 8: return 16;

case 9: return 31;

case 10: return 32;

case 11: return 63;

case 12: return 64;

case 13: return 255;

case 14: return 32768;

case 15: return 65535;

default: return 0;

}

}

:function:::FP_formats:convert_fmt_micromips:int fmt

*micromips32:

*micromips64:

{

switch (fmt)

{

case 0: return fmt_single;

case 1: return fmt_double;

case 2: return fmt_ps;

default: return fmt_unknown;

}

}

:function:::FP_formats:convert_fmt_micromips_cvt_d:int fmt

*micromips32:

*micromips64:

{

switch (fmt)

{

case 0: return fmt_single;

case 1: return fmt_word;

case 2: return fmt_long;

default: return fmt_unknown;

}

}

:function:::FP_formats:convert_fmt_micromips_cvt_s:int fmt

*micromips32:

*micromips64:

{

switch (fmt)

{

case 0: return fmt_double;

case 1: return fmt_word;

case 2: return fmt_long;

default: return fmt_unknown;

}

}

011011,3.RD,6.IMMEDIATE,1:POOL16E:16::ADDIUR1SP

"addiur1sp r<TRD>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

do_addiu (SD_, SPIDX, TRD, IMMEDIATE << 2);

}

011011,3.RD,3.RS,3.IMMEDIATE,0:POOL16E:16::ADDIUR2

"addiur2 r<TRD>, r<TRS>, <IMM_DEC1>"

*micromips32:

*micromips64:

{

do_addiu (SD_, TRS, TRD, IMM_DEC1);

}

010011,5.RD,4.IMMEDIATE,0:POOL16D:16::ADDIUS5

"addius5 r<RD>, <IMM_DEC2>"

*micromips32:

*micromips64:

{

do_addiu (SD_, RD, RD, IMM_DEC2);

}

010011,9.IMMEDIATE,1:POOL16D:16::ADDIUSP

"addiusp <IMM_DEC3>"

*micromips32:

*micromips64:

{

do_addiu (SD_, SPIDX, SPIDX, IMM_DEC3 << 2);

}

000001,3.RD,3.RT,3.RS,0:POOL16A:16::ADDU16

"addu16 r<TRD>, r<TRS>, r<TRT>"

*micromips32:

*micromips64:

{

do_addu (SD_, TRS, TRT, TRD);

}

001011,3.RD,3.RS,4.IMMEDIATE:MICROMIPS:16::ANDI16

"andi16 r<TRD>, r<TRS>, <IMM_DEC4>"

*micromips32:

*micromips64:

{

do_andi (SD_, TRS, TRD, IMM_DEC4);

}

010001,0010,3.RT,3.RS:POOL16C:16::AND16

"and16 r<TRT>, r<TRS>"

*micromips32:

*micromips64:

{

do_and (SD_, TRS, TRT, TRT);

}

110011,10.IMMEDIATE:MICROMIPS:16::B16

"b16 <IMMEDIATE>"

*micromips32:

*micromips64:

{

NIA = delayslot_micromips (SD_, NIA + (EXTEND11 (IMMEDIATE << 1)),

NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);

}

100011,3.RS,7.IMMEDIATE:MICROMIPS:16::BEQZ16

"beqz16 r<TRS>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

if (GPR[TRS] == 0)

NIA = delayslot_micromips (SD_, NIA + (EXTEND8 (IMMEDIATE << 1)),

NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);

}

101011,3.RS,7.IMMEDIATE:MICROMIPS:16::BNEZ16

"bnez16 r<TRS>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

if (GPR[TRS] != 0)

NIA = delayslot_micromips (SD_, NIA + (EXTEND8 (IMMEDIATE << 1)),

NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);

}

010001,101000,4.CODE:POOL16C:16::BREAK16

"break16 %#lx<CODE>"

*micromips32:

*micromips64:

{

do_break16 (SD_, instruction_0);

}

010001,01110,5.RS:POOL16C:16::JALR16

"jalr16 r<RS>"

*micromips32:

*micromips64:

{

NIA = do_micromips_jalr (SD_, RAIDX, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32);

}

010001,01111,5.RS:POOL16C:16::JALRS16

"jalrs16 r<RS>"

*micromips32:

*micromips64:

{

NIA = do_micromips_jalr (SD_, RAIDX, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16);

}

010001,01100,5.RS:POOL16C:16::JR16

"jr16 r<RS>"

*micromips32:

*micromips64:

{

NIA = process_isa_mode (SD_,

delayslot_micromips (SD_, GPR[RS], NIA, MICROMIPS_DELAYSLOT_SIZE_ANY));

}

010001,11000,5.IMMEDIATE:POOL16C:16::JRADDIUSP

"jraddiusp <IMMEDIATE>"

*micromips32:

*micromips64:

{

address_word temp = RA;

do_addiu (SD_, SPIDX, SPIDX, IMMEDIATE << 2);

NIA = process_isa_mode (SD_, temp);

}

010001,01101,5.RS:POOL16C:16::JRC

"jrc r<RS>"

*micromips32:

*micromips64:

{

NIA = process_isa_mode (SD_, GPR[RS]);

}

000010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LBU16

"lbu16 r<TRT>, <IMM_DEC5>(r<TBASE>)"

*micromips32:

*micromips64:

{

/* LBU can have a negative offset. As the offset argument to do_load is

unsigned we need to do the address calcuation before the function call so

that the load address has been correctly calculated */

GPR[TRT] = do_load (SD_, AccessLength_BYTE, GPR[TBASE] + IMM_DEC5, 0);

}

001010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LHU16

"lhu16 r<TRT>, <IMM_SHIFT_1BIT>(r<TBASE>)"

*micromips32:

*micromips64:

{

GPR[TRT] = do_load (SD_, AccessLength_HALFWORD, GPR[TBASE], IMM_SHIFT_1BIT);

}

111011,3.RD,7.IMMEDIATE:MICROMIPS:16::LI16

"li16 r<TRD>, <IMM_DEC6>"

*micromips32:

*micromips64:

{

GPR[TRD] = IMM_DEC6;

}

011010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LW16

"lw16 r<TRT>, <IMM_SHIFT_2BIT>(r<TBASE>)"

*micromips32:

*micromips64:

{

GPR[TRT] = EXTEND32 (

do_load (SD_, AccessLength_WORD, GPR[TBASE], IMM_SHIFT_2BIT));

}

:%s::::LWMREGS:int lwmregs

*micromips32:

*micromips64:

{

if (lwmregs == 3)

return "s0, s1, s2, s3, ra";

else if (lwmregs == 2)

return "s0, s1, s2, ra";

else if (lwmregs == 1)

return "s0, s1, ra";

else if (lwmregs == 0)

return "s0, ra";

else

return "";

}

010001,0100,2.LWMREGS,4.IMMEDIATE:POOL16C:16::LWM16

"lwm16 %s<LWMREGS>, <IMM_SHIFT_2BIT>(sp)"

*micromips32:

*micromips64:

{

int address = GPR[SPIDX] + IMM_SHIFT_2BIT;

int reg_offset;

for (reg_offset = 0; reg_offset <= LWMREGS; reg_offset++)

GPR[16 + reg_offset] = EXTEND32 (

do_load (SD_, AccessLength_WORD, address, reg_offset * 4));

RA = EXTEND32 (do_load (SD_, AccessLength_WORD, address, reg_offset * 4));

}

011001,3.RT,7.IMMEDIATE:MICROMIPS:16::LWGP

"lwgp r<TRT>, <IMM_SHIFT_2BIT>(gp)"

*micromips32:

*micromips64:

{

GPR[TRT] = EXTEND32 (

do_load (SD_, AccessLength_WORD, GPR[28], IMM_SHIFT_2BIT));

}

010010,5.RT,5.IMMEDIATE:MICROMIPS:16::LWSP

"lwsp r<RT>, <IMM_SHIFT_2BIT>(sp)"

*micromips32:

*micromips64:

{

GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMM_SHIFT_2BIT));

}

010001,10000,5.RD:POOL16C:16::MFHI16

"mfhi16 r<RD>"

*micromips32:

*micromips64:

{

do_mfhi (SD_, RD);

}

010001,10010,5.RD:POOL16C:16::MFLO16

"mflo16 r<RD>"

*micromips32:

*micromips64:

{

do_mflo (SD_, RD);

}

000011,5.RD,5.RS:MICROMIPS:16::MOVE16

"nop":RD==0&&RS==0

"move16 r<RD>, r<RS>"

*micromips32:

*micromips64:

{

GPR[RD] = GPR[RS];

}

:%s::::DESTREGS:int regs

*micromips32:

*micromips64:

{

switch (regs)

{

case 0: return "a1, a2,";

case 1: return "a1, a3,";

case 2: return "a2, a3,";

case 3: return "a0, s5,";

case 4: return "a0, s6,";

case 5: return "a0, a1,";

case 6: return "a0, a2,";

case 7: return "a0, a3,";

default: return "";

}

}

100001,3.DESTREGS,3.RT,3.RS,0:MICROMIPS:16::MOVEP

"movep %s<DESTREGS> r<ERS>, r<ERT>"

*micromips32:

*micromips64:

{

int rd;

int re;

int dest = DESTREGS;

if (dest == 0 || dest == 1)

rd = 5;

else if (dest == 2)

rd = 6;

else

rd = 4;

if (dest == 0 || dest == 6)

re = 6;

else if (dest == 1 || dest == 2 || dest == 7)

re = 7;

else if (dest == 3)

re = 21;

else if (dest == 4)

re = 22;

/* assume dest is 5 */

else

re = 5;

GPR[rd] = GPR[ERS];

GPR[re] = GPR[ERT];

}

010001,0000,3.RT,3.RS:POOL16C:16::NOT16

"not16 r<TRT>, r<TRS>"

*micromips32:

*micromips64:

{

do_nor (SD_, 0, TRS, TRT);

}

010001,0011,3.RT,3.RS:POOL16C:16::OR16

"or16 r<TRT>, r<TRS>"

*micromips32:

*micromips64:

{

do_or (SD_, TRS, TRT, TRT);

}

100010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SB16

"sb16 r<TRT_S>, <IMMEDIATE>(r<TBASE>)"

*micromips32:

*micromips64:

{

do_store (SD_, AccessLength_BYTE, GPR[TBASE], IMMEDIATE, GPR[TRT_S]);

}

010001,101100,4.CODE:POOL16C:16::SDBBP16

"sdbbp16 %#lx<CODE>"

*micromips32:

*micromips64:

{

SignalException (DebugBreakPoint, instruction_0);

}

101010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SH16

"sh16 r<TRT_S>, <IMM_SHIFT_1BIT>(r<TBASE>)"

*micromips32:

*micromips64:

{

do_store (SD_, AccessLength_HALFWORD, GPR[TBASE], IMM_SHIFT_1BIT, GPR[TRT_S]);

}

001001,3.RD,3.RT,3.SHIFT,0:POOL16B:16::SLL16

"sll16 r<TRD>, r<TRT>, <SHIFT_DEC>"

*micromips32:

*micromips64:

{

do_sll (SD_, TRT, TRD, SHIFT_DEC);

}

001001,3.RD,3.RT,3.SHIFT,1:POOL16B:16::SRL16

"srl16 r<TRD>, r<TRT>, <SHIFT_DEC>"

*micromips32:

*micromips64:

{

do_srl (SD_, TRT, TRD, SHIFT_DEC);

}

000001,3.RD,3.RT,3.RS,1:POOL16A:16::SUBU16

"subu16 r<TRD>, r<TRS>, r<TRT>"

*micromips32:

*micromips64:

{

do_subu (SD_, TRS, TRT, TRD);

}

111010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SW16

"sw16 r<TRT_S>, <IMM_SHIFT_2BIT>(r<TBASE>)"

*micromips32:

*micromips64:

{

do_store (SD_, AccessLength_WORD, GPR[TBASE], IMM_SHIFT_2BIT, GPR[TRT_S]);

}

110010,5.RT,5.IMMEDIATE:MICROMIPS:16::SWSP

"swsp r<RT>, <IMM_SHIFT_2BIT>(sp)"

*micromips32:

*micromips64:

{

do_store (SD_, AccessLength_WORD, SP, IMM_SHIFT_2BIT, GPR[RT]);

}

010001,0101,2.LWMREGS,4.IMMEDIATE:POOL16C:16::SWM16

"swm16 %s<LWMREGS>, <IMM_SHIFT_2BIT>(sp)"

*micromips32:

*micromips64:

{

int address = GPR[SPIDX] + IMM_SHIFT_2BIT;

int reg_offset;

for (reg_offset = 0; reg_offset <= LWMREGS; reg_offset++)

do_store (SD_, AccessLength_WORD, address, reg_offset * 4,

GPR[16 + reg_offset]);

do_store (SD_, AccessLength_WORD, address, reg_offset * 4, RA);

}

010001,0001,3.RT,3.RS:POOL16C:16::XOR16

"xor16 r<TRT>, r<TRS>"

*micromips32:

*micromips64:

{

do_xor (SD_, TRS, TRT, TRT);

}

000000,5.RT,5.RS,5.RD,00100,010000:POOL32A:32::ADD

"add r<RD>, r<RS>, r<RT>"

*micromips32:

*micromips64:

{

do_add (SD_, RS, RT, RD);

}

000100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ADDI

"addi r<RT>, r<RS>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

do_addi (SD_, RS, RT, IMMEDIATE);

}

001100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ADDIU

"li r<RT>, <IMMEDIATE>":RS==0

"addiu r<RT>, r<RS>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

do_addiu (SD_, RS, RT, IMMEDIATE);

}

011110,3.RS,23.IMMEDIATE:MICROMIPS:32::ADDIUPC

"addiupc r<TRS>, <IMM_SHIFT_2BIT>"

*micromips32:

*micromips64:

{

GPR[TRS] = EXTEND32 ((CIA & ~3) + EXTEND25 (IMM_SHIFT_2BIT));

}

000000,5.RT,5.RS,5.RD,00101,010000:POOL32A:32::ADDU

"addu r<RD>, r<RS>, r<RT>"

*micromips32:

*micromips64:

{

do_addu (SD_, RS, RT, RD);

}

000000,5.RT,5.RS,5.RD,01001,010000:POOL32A:32::AND

"and r<RD>, r<RS>, r<RT>"

*micromips32:

*micromips64:

{

do_and (SD_, RS, RT, RD);

}

110100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ANDI

"andi r<RT>, r<RS>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

do_andi (SD_, RS, RT, IMMEDIATE);

}

010000,1110,1.TF,3.CC,00,16.IMMEDIATE:POOL32I:32,f::BC1a

"bc1%s<TF> <IMMEDIATE>":CC == 0

"bc1%s<TF> <CC>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

check_fpu (SD_);

if (GETFCC(CC) == TF)

{

address_word dest = NIA + (EXTEND16 (IMMEDIATE) << 1);

NIA = delayslot_micromips (SD_, dest, NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);

}

}

010000,1010,1.TF,3.CC,00,16.IMMEDIATE:POOL32I:32::BC2a

"bc2%s<TF> <CC>, <IMMEDIATE>":CC == 0

"bc2%s<TF> <CC>, <IMMEDIATE>"

*micromips32:

*micromips64:

100101,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::BEQ

"b <IMMEDIATE>":RT == 0 && RS == 0

"beq r<RS>, r<RT>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

address_word offset = EXTEND16 (IMMEDIATE) << 1;

if ((signed_word) GPR[RS] == (signed_word) GPR[RT])

NIA = delayslot_micromips (SD_, NIA + offset, NIA,

MICROMIPS_DELAYSLOT_SIZE_ANY);

}

010000,00010,5.RS,16.IMMEDIATE:POOL32I:32::BGEZ

"bgez r<RS>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

address_word offset = EXTEND16 (IMMEDIATE) << 1;

if ((signed_word) GPR[RS] >= 0)

NIA = delayslot_micromips (SD_, NIA + offset, NIA,

MICROMIPS_DELAYSLOT_SIZE_ANY);

}

010000,00111,5.RS,16.IMMEDIATE:POOL32I:32::BEQZC

"beqzc r<RS>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

address_word offset = EXTEND16 (IMMEDIATE) << 1;

if (GPR[RS] == 0)

NIA = NIA + offset;

}

010000,00011,5.RS,16.IMMEDIATE:POOL32I:32::BGEZAL

"bal <IMMEDIATE>":RS == 0

"bgezal r<RS>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

address_word offset = EXTEND16 (IMMEDIATE) << 1;

if (RS == 31)

Unpredictable ();

RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_32) | ISA_MODE_MICROMIPS;

if ((signed_word) GPR[RS] >= 0)

NIA = delayslot_micromips (SD_, NIA + offset, NIA,

MICROMIPS_DELAYSLOT_SIZE_32);

}

010000,00110,5.RS,16.IMMEDIATE:POOL32I:32::BGTZ

"bgtz r<RS>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

address_word offset = EXTEND16 (IMMEDIATE) << 1;

if ((signed_word) GPR[RS] > 0)

NIA = delayslot_micromips (SD_, NIA + offset, NIA,

MICROMIPS_DELAYSLOT_SIZE_ANY);

}

010000,10011,5.RS,16.IMMEDIATE:POOL32I:32::BGEZALS

"bal <IMMEDIATE>":RS == 0

"bgezals r<RS>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

address_word offset = EXTEND16 (IMMEDIATE) << 1;

if (RS == 31)

Unpredictable ();

RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_16) | ISA_MODE_MICROMIPS;

if ((signed_word) GPR[RS] >= 0)

NIA = delayslot_micromips (SD_, NIA + offset, NIA,

MICROMIPS_DELAYSLOT_SIZE_16);

}

010000,00100,5.RS,16.IMMEDIATE:POOL32I:32::BLEZ

"blez r<RS>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

address_word offset = EXTEND16 (IMMEDIATE) << 1;

/* NOTE: The branch occurs AFTER the next instruction has been

executed */

if ((signed_word) GPR[RS] <= 0)

NIA = delayslot_micromips (SD_, NIA + offset, NIA,

MICROMIPS_DELAYSLOT_SIZE_ANY);

}

010000,00000,5.RS,16.IMMEDIATE:POOL32I:32::BLTZ

"bltz r<RS>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

address_word offset = EXTEND16 (IMMEDIATE) << 1;

if ((signed_word) GPR[RS] < 0)

NIA = delayslot_micromips (SD_, NIA + offset, NIA,

MICROMIPS_DELAYSLOT_SIZE_ANY);

}

010000,00001,5.RS,16.IMMEDIATE:POOL32I:32::BLTZAL

"bltzal r<RS>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

address_word offset = EXTEND16 (IMMEDIATE) << 1;

if (RS == 31)

Unpredictable ();

RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_32) | ISA_MODE_MICROMIPS;

/* NOTE: The branch occurs AFTER the next instruction has been

executed */

if ((signed_word) GPR[RS] < 0)

NIA = delayslot_micromips (SD_, NIA + offset, NIA,

MICROMIPS_DELAYSLOT_SIZE_32);

}

010000,10001,5.RS,16.IMMEDIATE:POOL32I:32::BLTZALS

"bltzals r<RS>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

address_word offset = EXTEND16 (IMMEDIATE) << 1;

if (RS == 31)

Unpredictable ();

RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_16) | ISA_MODE_MICROMIPS;

if ((signed_word) GPR[RS] < 0)

NIA = delayslot_micromips (SD_, NIA + offset, NIA,

MICROMIPS_DELAYSLOT_SIZE_16);

}

101101,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::BNE

"bne r<RS>, r<RT>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

address_word offset = EXTEND16 (IMMEDIATE) << 1;

if ((signed_word) GPR[RS] != (signed_word) GPR[RT])

NIA = delayslot_micromips (SD_, NIA + offset, NIA,

MICROMIPS_DELAYSLOT_SIZE_ANY);

}

010000,00101,5.RS,16.IMMEDIATE:POOL32I:32::BNEZC

"bnezc r<RS>, <IMMEDIATE>"

*micromips32:

*micromips64:

{

address_word offset = EXTEND16 (IMMEDIATE) << 1;

if ((signed_word) GPR[RS] != 0)

NIA = NIA + offset;

}

000000,20.CODE,000111:POOL32A:32::BREAK

"break %#lx<CODE>"

*micromips32:

*micromips64:

{

do_break (SD_, instruction_0);

}

001000,5.OP,5.BASE,0110,12.IMMEDIATE:POOL32B:32::CACHE

"cache <OP>, <IMMEDIATE>(r<BASE>)"

*micromips32:

*micromips64:

{

address_word base = GPR[BASE];

address_word offset = EXTEND12 (IMMEDIATE);

address_word vaddr = loadstore_ea (SD_, base, offset);

address_word paddr = vaddr;

CacheOp (OP, vaddr, paddr, instruction_0);

}

011000,5.OP,5.BASE,1010011,9.IMMEDIATE:POOL32C:32::CACHEE

"cachee <OP>, <IMMEDIATE>(r<BASE>)"

*micromips32:

*micromips64:

010101,5.RT,5.FS,0001000000,111011:POOL32F:32,f::CFC1

"cfc1 r<RT>, f<FS>"

*micromips32:

*micromips64:

{

do_cfc1 (SD_, RT, FS);

}

000000,5.RT,5.IMPL,1100110100,111100:POOL32A:32::CFC2

"cfc2 r<RT>, <IMPL>"

*micromips32:

*micromips64:

000000,5.RT,5.RS,0100101100,111100:POOL32A:32::CLO

"clo r<RT>, r<RS>"

*micromips32:

*micromips64:

{

do_clo (SD_, RT, RS);

}

000000,5.RT,5.RS,0101101100,111100:POOL32A:32::CLZ

"clz r<RT>, r<RS>"

*micromips32:

*micromips64:

{

do_clz (SD_, RT, RS);

}

000000,23.COFUN,010:POOL32A:32::COP2

"cop2 <COFUN>"

*micromips32:

*micromips64:

010101,5.RT,5.FS,0001100000,111011:POOL32F:32,f::CTC1

"ctc1 r<RT>, f<FS>"

*micromips32:

*micromips64:

{

do_ctc1 (SD_, RT, FS);

}

000000,5.RT,5.IMPL,1101110100,111100:POOL32A:32::CTC2

"ctc2 r<RT>, <IMPL>"

*micromips32:

*micromips64:

000000,00000000001110001101,111100:POOL32A:32::DERET

"deret"

*micromips32:

*micromips64:

000000,00000,5.RS,0100011101,111100:POOL32A:32::DI

"di":RS == 0

"di r<RS>"

*micromips32:

*micromips64:

{

do_di (SD_, RS);

}

000000,5.RT,5.RS,1010101100,111100:POOL32A:32::DIV

"div r<RS>, r<RT>"

*micromips32:

*micromips64:

{

do_div (SD_, RS, RT);

}

000000,5.RT,5.RS,1011101100,111100:POOL32A:32::DIVU

"divu r<RS>, r<RT>"

*micromips32:

*micromips64:

{

do_divu (SD_, RS, RT);

}

000000,00000000000001100000,000000:POOL32A:32::EHB

"ehb"

*micromips32:

*micromips64:

000000,00000,5.RS,0101011101,111100:POOL32A:32::EI

"ei":RS == 0

"ei r<RS>"

*micromips32:

*micromips64:

{

do_ei (SD_, RS);

}

000000,00000000001111001101,111100:POOL32A:32::ERET

"eret"

*micromips32:

*micromips64:

{

if (SR & status_ERL)

{

/* Oops, not yet available */

sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");

NIA = EPC;

SR &= ~status_ERL;

}

else

{

NIA = EPC;

SR &= ~status_EXL;

}

}

000000,5.RT,5.RS,5.MSBD,5.LSB,101100:POOL32A:32::EXT