2016-12-31 Alan Modra <[email protected]>

* disassemble.c (disassembler): Add break accidentally removed

by PRU patch.

2016-12-31 Dimitar Dimitrov <[email protected]>

* Makefile.am: Add PRU source files.

* configure.ac: Add PRU target.

* disassemble.c (disassembler): Register PRU arch.

* pru-dis.c: New file.

* pru-opc.c: New file.

* Makefile.in: Regenerate.

* configure: Regenerate.

2016-12-29 Yao Qi <[email protected]>

* avr-dis.c: Include "bfd_stdint.h"

(avrdis_opcode): Change return type to int, add argument

insn. Set *INSN on success.

(print_insn_avr): Check return value of avrdis_opcode, and

return -1 on error.

2016-12-28 Alan Modra <[email protected]>

* configure.ac: Revert 2016-12-23.

* Makefile.am: Likewise.

(MIPS_DEFS): Define.

(mips-dis.lo): Add rule.

* Makefile.in: Regenerate.

* aclocal.m4: Regenerate.

* config.in: Regenerate.

* configure: Regenerate.

2016-12-23 Maciej W. Rozycki <[email protected]>

* mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3',

`4' and `s' operand codes.

(mips16_opcodes): Add "asmacro" entry.

2016-12-23 Maciej W. Rozycki <[email protected]>

* mips-dis.c (print_mips16_insn_arg): Simplify processing of

extended operands.

* mips16-opc.c (decode_mips16_operand): Switch the extended

form of the `<' operand type to LSB position 22.

2016-12-23 Maciej W. Rozycki <[email protected]>

* mips16-opc.c (decode_mips16_operand): Replace `0' and `4'

operand codes with `.' and `F' respectively.

(mips16_opcodes): Likewise.

2016-12-23 Maciej W. Rozycki <[email protected]>

* mips-dis.c (print_insn_mips16): Disallow EXTEND prefix

matching for INSN2_SHORT_ONLY opcode table entries.

* mips16-opc.c (SH): New macro.

(mips16_opcodes): Set SH in `pinfo2' for non-extensible

instruction entries: "nop", "addu", "and", "break", "cmp",

"daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",

"drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",

"dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",

"jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",

"not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",

"srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",

"seh", "sew", "zeb", "zeh", "zew" and "extend".

2016-12-23 Maciej W. Rozycki <[email protected]>

* mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended

encoding support.

2016-12-23 Maciej W. Rozycki <[email protected]>

* mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for

"extend".

2016-12-23 Maciej W. Rozycki <[email protected]>

* mips-dis.c (set_default_mips_dis_options): Use

HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the

call to `bfd_mips_elf_get_abiflags'.

* configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD.

* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'.

* aclocal.m4: Regenerate.

* configure: Regenerate.

* config.in: Regenerate.

* Makefile.in: Regenerate.

2016-12-23 Tristan Gingold <[email protected]>

* configure: Regenerate.

2016-12-23 Tristan Gingold <[email protected]>

* po/opcodes.pot: Regenerate.

2016-12-21 Andrew Waterman <[email protected]>

* riscv-opc.c (riscv_opcodes): Reorder jal and call entries.

2016-12-20 Maciej W. Rozycki <[email protected]>

* mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than

ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.

(print_insn_mips16): Check opcode entries for validity against

the ISA level and ASE set selected.

2016-12-20 Maciej W. Rozycki <[email protected]>

* mips-dis.c (print_mips16_insn_arg): Always handle `extend' and

`insn' together, with `extend' as the high-order 16 bits.

(match_kind): New enum.

(print_insn_mips16): Rework for 32-bit instruction matching.

Do not dump EXTEND prefixes here.

* mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.

Recode `match' and `mask' fields as 32-bit in absolute "jal" and

"jalx" entries.

2016-12-20 Maciej W. Rozycki <[email protected]>

* mips16-opc.c (mips16_opcodes): Set membership to I3 rather

than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"

INSN_MACRO entries.

2016-12-20 Maciej W. Rozycki <[email protected]>

* mips16-opc.c (mips16_opcodes): Set membership to I3 rather

than I1 for the SP-relative "sd"/$ra entry (SDRASP minor

opcode).

2016-12-20 Andrew Waterman <[email protected]>

* riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to

"*.aqrl".

2016-12-20 Andrew Waterman <[email protected]>

* riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as

INSN_ALIAS.

2016-12-20 Andrew Waterman <[email protected]>

* riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"

format.

2016-12-20 Andrew Waterman <[email protected]>

* riscv-dis.c (riscv_disassemble_insn): Default to the ELF's

XLEN when none is provided.

2016-12-20 Andrew Waterman <[email protected]>

* riscv-opc.c: Formatting fixes.

2016-12-20 Alan Modra <[email protected]>

* Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.

* Makefile.in: Regenerate.

* po/POTFILES.in: Regenerate.

2016-12-19 Maciej W. Rozycki <[email protected]>

* mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:

Only examine ELF file structures here.

2016-12-19 Maciej W. Rozycki <[email protected]>

* mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call

`bfd_mips_elf_get_abiflags' here.

2016-12-16 Nick Clifton <[email protected]>

* arm-dis.c (print_insn_thumb32): Fix compile time warning

computing value_in_comment.

2016-12-14 Maciej W. Rozycki <[email protected]>

* mips-dis.c (mips_convert_abiflags_ases): New function.

(set_default_mips_dis_options): Also infer ASE flags from ELF

file structures.

2016-12-14 Maciej W. Rozycki <[email protected]>

* mips-dis.c (set_default_mips_dis_options): Reorder ELF file

header flag interpretation code.

2016-12-14 Maciej W. Rozycki <[email protected]>

* mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in

`pinfo2' with SP-relative "sd" entries.

2016-12-14 Maciej W. Rozycki <[email protected]>

* mips16-opc.c (mips16_opcodes): Update comments on MIPS16e

compact jumps.

2016-12-13 Renlin Li <[email protected]>

* aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range

qualifier.

(operand_general_constraint_met_p): Remove case for CP_REG.

(aarch64_print_operand): Print CRn, CRm operand using imm field.

* aarch64-tbl.h (QL_SYS): Use CR qualifier.

(QL_SYSL): Likewise.

(aarch64_opcode_table): Change CRn, CRm operand class and type.

* aarch64-opc-2.c : Regenerate.

* aarch64-asm-2.c : Likewise.

* aarch64-dis-2.c : Likewise.

2016-12-12 Yao Qi <[email protected]>

* rx-dis.c: Include <setjmp.h>

(struct private): New.

(rx_get_byte): Check return value of read_memory_func, and

call memory_error_func and OPCODES_SIGLONGJMP on error.

(print_insn_rx): Call OPCODES_SIGSETJMP.

2016-12-12 Yao Qi <[email protected]>

* rl78-dis.c: Include <setjmp.h>.

(struct private): New.

(rl78_get_byte): Check return value of read_memory_func, and

call memory_error_func and OPCODES_SIGLONGJMP on error.

(print_insn_rl78_common): Call OPCODES_SIGJMP.

2016-12-09 Maciej W. Rozycki <[email protected]>

* mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.

2016-12-09 Maciej W. Rozycki <[email protected]>

* mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather

than UINT.

2016-12-09 Maciej W. Rozycki <[email protected]>

* mips-dis.c (print_insn_mips16): Use a tab rather than a space

to separate `extend' and its uninterpreted argument output.

Separate hexadecimal halves of undecoded extended instructions

output.

2016-12-08 Maciej W. Rozycki <[email protected]>

* mips-dis.c (print_mips16_insn_arg): Remove extraneous

indentation space across.

2016-12-08 Maciej W. Rozycki <[email protected]>

* mips-dis.c (print_mips16_insn_arg): Avoid delay-slot

adjustment for PC-relative operations following MIPS16e compact

jumps or undefined RR/J(AL)R(C) encodings.

2016-12-08 Maciej W. Rozycki <[email protected]>

* aarch64-asm.c (aarch64_ins_reglane): Rename `index' local

variable to `reglane_index'.

2016-12-08 Luis Machado <[email protected]>

* ppc-dis.c (get_powerpc_dialect): Check NULL info->section.

2016-12-07 Maciej W. Rozycki <[email protected]>

* mips-dis.c (print_mips16_insn_arg): Fix comment typo.

2016-12-07 Maciej W. Rozycki <[email protected]>

* mips16-opc.c (mips16_opcodes): Update comment naming structure

members.

2016-12-07 Maciej W. Rozycki <[email protected]>

* mips-dis.c (print_mips_disassembler_options): Reformat output.

2016-12-05 Szabolcs Nagy <[email protected]>

* arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.

(print_insn_coprocessor): Add 'V' format for neon D or Q regs.

2016-12-05 Szabolcs Nagy <[email protected]>

* arm-dis.c (coprocessor_opcodes): Add vjcvt.

2016-12-01 Nick Clifton <[email protected]>

PR binutils/20893

* i386-dis.c (OP_VEX): Replace call to abort with a append of bad

opcode designator.

2016-11-29 Claudiu Zissulescu <[email protected]>

* arc-opc.c (insert_ra_chk): New function.

(insert_rb_chk): Likewise.

(insert_rad): Update text error message.

(insert_rcd): Likewise.

(insert_rhv2): Likewise.

(insert_r0): Likewise.

(insert_r1): Likewise.

(insert_r2): Likewise.

(insert_r3): Likewise.

(insert_sp): Likewise.

(insert_gp): Likewise.

(insert_pcl): Likewise.

(insert_blink): Likewise.

(insert_ilink1): Likewise.

(insert_ilink2): Likewise.

(insert_ras): Likewise.

(insert_rbs): Likewise.

(insert_rcs): Likewise.

(insert_simm3s): Likewise.

(insert_rrange): Likewise.

(insert_fpel): Likewise.

(insert_blinkel): Likewise.

(insert_pcel): Likewise.

(insert_nps_3bit_dst): Likewise.

(insert_nps_3bit_dst_short): Likewise.

(insert_nps_3bit_src2_short): Likewise.

(insert_nps_bitop_size_2b): Likewise.

(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.

(RA_CHK): Define.

(RB): Adjust.

(RB_CHK): Define.

(RC): Adjust.

* arc-dis.c (print_insn_arc): Add LOAD and STORE class.

* arc-tbl.h (div, divu): All instructions are DIVREM class.

Change first insn argument to check for LP_COUNT usage.

(rem): Likewise.

(ld, ldd): All instructions are LOAD class. Change first insn

argument to check for LP_COUNT usage.

(st, std): All instructions are STORE class.

(mac, mpy, dmac, mul, dmpy): All instructions are MPY class.

Change first insn argument to check for LP_COUNT usage.

(mov): All instructions are MOVE class. Change first insn

argument to check for LP_COUNT usage.

2016-11-29 Claudiu Zissulescu <[email protected]>

* arc-dis.c (is_compatible_p): Remove function.

(skip_this_opcode): Don't add any decoding class to decode list.

Remove warning.

(find_format_from_table): Go through all opcodes, and warn if we

use a guessed mnemonic.

2016-11-28 Ramiro Polla <[email protected]>

Amit Pawar <[email protected]>

PR binutils/20637

* i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP

instructions.

2016-11-22 Ambrogino Modigliani <[email protected]>

* configure: Regenerate.

2016-11-22 Jose E. Marchesi <[email protected]>

* sparc-opc.c (HWS_V8): Definition moved from

gas/config/tc-sparc.c.

(HWS_V9): Likewise.

(HWS_VA): Likewise.

(HWS_VB): Likewise.

(HWS_VC): Likewise.

(HWS_VD): Likewise.

(HWS_VE): Likewise.

(HWS_VV): Likewise.

(HWS_VM): Likewise.

(HWS2_VM): Likewise.

(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of

existing entries.

2016-11-22 Claudiu Zissulescu <[email protected]>

* arc-tbl.h: Reorder conditional flags with delay flags for 'b'

instructions.

2016-11-18 Szabolcs Nagy <[email protected]>

* aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.

(aarch64_feature_simd_v8_3, SIMD_V8_3): Define.

(aarch64_opcode_table): Add fcmla and fcadd.

(AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.

* aarch64-asm.h (aarch64_ins_imm_rotate): Declare.

* aarch64-asm.c (aarch64_ins_imm_rotate): Define.

* aarch64-dis.h (aarch64_ext_imm_rotate): Declare.

* aarch64-dis.c (aarch64_ext_imm_rotate): Define.

* aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.

* aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.

(operand_general_constraint_met_p): Rotate and index range check.

(aarch64_print_operand): Handle rotate operand.

* aarch64-asm-2.c: Regenerate.

* aarch64-dis-2.c: Likewise.

* aarch64-opc-2.c: Likewise.

2016-11-18 Szabolcs Nagy <[email protected]>

* aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.

* aarch64-asm-2.c: Regenerate.

* aarch64-dis-2.c: Regenerate.

* aarch64-opc-2.c: Regenerate.

2016-11-18 Szabolcs Nagy <[email protected]>

* aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.

(QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.

* aarch64-asm-2.c: Regenerate.

* aarch64-dis-2.c: Regenerate.

* aarch64-opc-2.c: Regenerate.

2016-11-18 Szabolcs Nagy <[email protected]>

* aarch64-tbl.h (QL_X1NIL): New.

(arch64_opcode_table): Add ldraa, ldrab.

(AARCH64_OPERANDS): Add "ADDR_SIMM10".

* aarch64-asm.h (aarch64_ins_addr_simm10): Declare.

* aarch64-asm.c (aarch64_ins_addr_simm10): Define.

* aarch64-dis.h (aarch64_ext_addr_simm10): Declare.

* aarch64-dis.c (aarch64_ext_addr_simm10): Define.

* aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.

* aarch64-opc.c (fields): Add data for FLD_S_simm10.

(operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.

(aarch64_print_operand): Likewise.

* aarch64-asm-2.c: Regenerate.

* aarch64-dis-2.c: Regenerate.

* aarch64-opc-2.c: Regenerate.

2016-11-11 Szabolcs Nagy <[email protected]>

* aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,

brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.

* aarch64-asm-2.c: Regenerate.

* aarch64-dis-2.c: Regenerate.

* aarch64-opc-2.c: Regenerate.

2016-11-11 Szabolcs Nagy <[email protected]>

* aarch64-tbl.h (arch64_opcode_table): Add pacga.

(AARCH64_OPERANDS): Add Rm_SP.

* aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.

* aarch64-asm-2.c: Regenerate.

* aarch64-dis-2.c: Regenerate.

* aarch64-opc-2.c: Regenerate.

2016-11-11 Szabolcs Nagy <[email protected]>

* aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,

autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,

autdzb, xpaci, xpacd.

* aarch64-asm-2.c: Regenerate.

* aarch64-dis-2.c: Regenerate.

* aarch64-opc-2.c: Regenerate.

2016-11-11 Szabolcs Nagy <[email protected]>

* aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,

apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,

apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.

(aarch64_sys_reg_supported_p): Add feature test for new registers.

2016-11-11 Szabolcs Nagy <[email protected]>

* aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.

(arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,

autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,

autibsp.

* aarch64-asm-2.c: Regenerate.

* aarch64-dis-2.c: Regenerate.

2016-11-11 Szabolcs Nagy <[email protected]>

* aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.

2016-11-09 H.J. Lu <[email protected]>

PR binutils/20799

* i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.

* i386-dis.c (EdqwS): Removed.

(dqw_swap_mode): Likewise.

(intel_operand_size): Don't check dqw_swap_mode.

(OP_E_register): Likewise.

(OP_E_memory): Likewise.

(OP_G): Likewise.

(OP_EX): Likewise.

* i386-opc.tbl: Remove "S" from EVEX vpextrw.

* i386-tbl.h: Regerated.

2016-11-09 H.J. Lu <[email protected]>

* i386-opc.tbl: Merge AVX512F vmovq.

* i386-tbl.h: Regerated.

2016-11-08 H.J. Lu <[email protected]>

PR binutils/20701

* i386-dis.c (THREE_BYTE_0F7A): Removed.

(dis386_twobyte): Don't use THREE_BYTE_0F7A.

(three_byte_table): Remove THREE_BYTE_0F7A.

2016-11-07 H.J. Lu <[email protected]>

PR binutils/20775

* i386-dis.c (FGRPd9_2): Replace 0 with 1.

(FGRPd9_4): Replace 1 with 2.

(FGRPd9_5): Replace 2 with 3.

(FGRPd9_6): Replace 3 with 4.

(FGRPd9_7): Replace 4 with 5.

(FGRPda_5): Replace 5 with 6.

(FGRPdb_4): Replace 6 with 7.

(FGRPde_3): Replace 7 with 8.

(FGRPdf_4): Replace 8 with 9.

(fgrps): Add an entry for Bad_Opcode.

2016-11-04 Andrew Burgess <[email protected]>

* arc-opc.c (arc_flag_operands): Add F_DI14.

(arc_flag_classes): Add C_DI14.

* arc-nps400-tbl.h: Add new exc instructions.

2016-11-03 Graham Markall <[email protected]>

* arc-dis.c (arc_insn_length): Return length 8 for instructions with

major opcode 0xa.

* arc-nps-400-tbl.h: Add dcmac instruction.

* arc-opc.c (arc_operands): Added operands for dcmac instruction.

(insert_nps_rbdouble_64): Added.

(extract_nps_rbdouble_64): Added.

(insert_nps_proto_size): Added.

(extract_nps_proto_size): Added.

2016-11-03 Andrew Burgess <[email protected]>

* arc-dis.c (struct arc_operand_iterator): Remove all fields

relating to long instruction processing, add new limm field.

(OPCODE): Rename to...

(OPCODE_32BIT_INSN): ...this.

(OPCODE_AC): Delete.

(skip_this_opcode): Handle different instruction lengths, update

macro name.

(special_flag_p): Update parameter type.

(find_format_from_table): Update for more instruction lengths.

(find_format_long_instructions): Delete.

(find_format): Update for more instruction lengths.

(arc_insn_length): Likewise.

(extract_operand_value): Update for more instruction lengths.

(operand_iterator_next): Remove code relating to long

instructions.

(arc_opcode_to_insn_type): New function.

(print_insn_arc):Update for more instructions lengths.

* arc-ext.c (extInstruction_t): Change argument type.

* arc-ext.h (extInstruction_t): Change argument type.

* arc-fxi.h: Change type unsigned to unsigned long long

extensively throughout.

* arc-nps400-tbl.h: Add long instructions taken from

arc_long_opcodes table in arc-opc.c.

* arc-opc.c: Update parameter types on insert/extract handlers.

(arc_long_opcodes): Delete.

(arc_num_long_opcodes): Delete.

(arc_opcode_len): Update for more instruction lengths.

2016-11-03 Graham Markall <[email protected]>

* arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.

2016-11-03 Graham Markall <[email protected]>

* arc-dis.c (find_format_from_table): Replace use of ARC_SHORT

with arc_opcode_len.

(find_format_long_instructions): Likewise.

* arc-opc.c (arc_opcode_len): New function.

2016-11-03 Andrew Burgess <[email protected]>

* arc-nps400-tbl.h: Fix some instruction masks.

2016-11-03 H.J. Lu <[email protected]>

* i386-dis.c (REG_82): Removed.

(X86_64_82_REG_0): Likewise.

(X86_64_82_REG_1): Likewise.

(X86_64_82_REG_2): Likewise.

(X86_64_82_REG_3): Likewise.

(X86_64_82_REG_4): Likewise.

(X86_64_82_REG_5): Likewise.

(X86_64_82_REG_6): Likewise.

(X86_64_82_REG_7): Likewise.

(X86_64_82): New.

(dis386): Use X86_64_82 instead of REG_82.

(reg_table): Remove REG_82.

(x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,

X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,

X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and

X86_64_82_REG_7.

2016-11-03 H.J. Lu <[email protected]>

PR binutils/20754

* i386-dis.c (REG_82): New.

(X86_64_82_REG_0): Likewise.

(X86_64_82_REG_1): Likewise.

(X86_64_82_REG_2): Likewise.

(X86_64_82_REG_3): Likewise.

(X86_64_82_REG_4): Likewise.

(X86_64_82_REG_5): Likewise.

(X86_64_82_REG_6): Likewise.

(X86_64_82_REG_7): Likewise.

(dis386): Use REG_82.

(reg_table): Add REG_82.

(x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,

X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,

X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.

2016-11-03 H.J. Lu <[email protected]>

* i386-dis.c (REG_82): Renamed to ...

(REG_83): This.

(dis386): Updated.

(reg_table): Likewise.

2016-11-02 Igor Tsimbalist <[email protected]>

* i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.

* i386-dis-evex.h (evex_table): Updated.

* i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,

CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.

(cpu_flags): Add CpuAVX512_4VNNIW.

* i386-opc.h (enum): (AVX512_4VNNIW): New.

(i386_cpu_flags): Add cpuavx512_4vnniw.

* i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.

* i386-init.h: Regenerate.

* i386-tbl.h: Ditto.

2016-11-02 Igor Tsimbalist <[email protected]>

* i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,

PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.

* i386-dis-evex.h (evex_table): Updated.

* i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,

CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.

(cpu_flags): Add CpuAVX512_4FMAPS.

(opcode_modifiers): Add ImplicitQuadGroup modifier.

* i386-opc.h (AVX512_4FMAP): New.

(i386_cpu_flags): Add cpuavx512_4fmaps.

(ImplicitQuadGroup): New.

(i386_opcode_modifier): Add implicitquadgroup.

* i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.

* i386-init.h: Regenerate.

* i386-tbl.h: Ditto.

2016-11-01 Palmer Dabbelt <[email protected]>

Andrew Waterman <[email protected]>

Add support for RISC-V architecture.

* configure.ac: Add entry for bfd_riscv_arch.

* configure: Regenerate.

* disassemble.c (disassembler): Add support for riscv.

(disassembler_usage): Likewise.

* riscv-dis.c: New file.

* riscv-opc.c: New file.

2016-10-21 H.J. Lu <[email protected]>

* i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.

(prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.

(rm_table): Update the RM_0FAE_REG_7 entry.

* i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.

(cpu_flags): Remove CpuPCOMMIT.

* i386-opc.h (CpuPCOMMIT): Removed.

(i386_cpu_flags): Remove cpupcommit.

* i386-opc.tbl: Remove pcommit.

* i386-init.h: Regenerated.

* i386-tbl.h: Likewise.

2016-10-20 H.J. Lu <[email protected]>

PR binutis/20705

* i386-dis.c (get_valid_dis386): Ignore the REX_B bit and

the highest bit in VEX.vvvv for the 3-byte VEX prefix in

32-bit mode. Don't check vex.register_specifier in 32-bit

mode.

(OP_VEX): Check for invalid mask registers.

2016-10-18 H.J. Lu <[email protected]>

PR binutis/20699

* i386-dis.c (OP_E_memory): Check addr32flag in stead of

sizeflag.

2016-10-18 H.J. Lu <[email protected]>

PR binutis/20704

* i386-dis.c (three_byte_table): Remove the remaining SSE5 support.

2016-10-18 Maciej W. Rozycki <[email protected]>

* aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'

local variable to `index_regno'.

2016-10-17 Cupertino Miranda <[email protected]>

* arc-tbl.h: Removed any "inv.+" instructions from the table.

2016-10-14 Claudiu Zissulescu <[email protected]>

* arc-dis.c (find_format_from_table): Discriminate LIMM indicator

usage on ISA basis.

2016-10-11 Jiong Wang <[email protected]>

PR target/20666

* aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.

2016-10-07 Jiong Wang <[email protected]>

PR target/20667

* aarch64-opc.c (aarch64_print_operand): Always print operand if it's

available.

2016-10-07 Alan Modra <[email protected]>

* sh-opc.h (sh_merge_bfd_arch): Delete prototype.

2016-10-06 Alan Modra <[email protected]>

* aarch64-opc.c: Spell fall through comments consistently.

* i386-dis.c: Likewise.

* aarch64-dis.c: Add missing fall through comments.

* aarch64-opc.c: Likewise.

* arc-dis.c: Likewise.

* arm-dis.c: Likewise.

* i386-dis.c: Likewise.

* m68k-dis.c: Likewise.

* mep-asm.c: Likewise.

* ns32k-dis.c: Likewise.

* sh-dis.c: Likewise.

* tic4x-dis.c: Likewise.

* tic6x-dis.c: Likewise.

* vax-dis.c: Likewise.

2016-10-06 Alan Modra <[email protected]>

* arc-ext.c (create_map): Add missing break.

* msp430-decode.opc (encode_as): Likewise.

* msp430-decode.c: Regenerate.

2016-10-06 Alan Modra <[email protected]>

* cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.

* crx-dis.c (print_insn_crx): Likewise.

2016-09-30 H.J. Lu <[email protected]>

PR binutils/20657

* i386-dis.c (putop): Don't assign alt twice.

2016-09-29 Jiong Wang <[email protected]>

PR target/20553

* aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.

2016-09-29 Alan Modra <[email protected]>

* ppc-opc.c (L): Make compulsory.

(LOPT): New, optional form of L.

(HTM_R): Define as LOPT.

(L0, L1): Delete.

(L32OPT): New, optional for 32-bit L.

(L2OPT): New, 2-bit L for dcbf.

(SVC_LEC): Update.

(L2): Define.

(insert_l0, extract_l0, insert_l1, extract_l2): Delete.

(powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.

<dcbf>: Use L2OPT.

<tlbiel, tlbie>: Use LOPT.

<wclr, wclrall>: Use L2.

2016-09-26 Vlad Zakharov <[email protected]>

* Makefile.in: Regenerate.

* configure: Likewise.

2016-09-26 Claudiu Zissulescu <[email protected]>

* arc-ext-tbl.h (EXTINSN2OPF): Define.

(EXTINSN2OP): Use EXTINSN2OPF.

(bspeekm, bspop, modapp): New extension instructions.

* arc-opc.c (F_DNZ_ND): Define.

(F_DNZ_D): Likewise.

(F_SIZEB1): Changed.

(C_DNZ_D): Define.

(C_HARD): Changed.

* arc-tbl.h (dbnz): New instruction.

(prealloc): Allow it for ARC EM.

(xbfu): Likewise.

2016-09-21 Richard Sandiford <[email protected]>

* aarch64-opc.c (print_immediate_offset_address): Print spaces

after commas in addresses.

(aarch64_print_operand): Likewise.

2016-09-21 Richard Sandiford <[email protected]>

* aarch64-opc.c (operand_general_constraint_met_p): Use "must be"

rather than "should be" or "expected to be" in error messages.

2016-09-21 Richard Sandiford <[email protected]>

* aarch64-dis.c (remove_dot_suffix): New function, split out from...

(print_mnemonic_name): ...here.

(print_comment): New function.

(print_aarch64_insn): Call it.

* aarch64-opc.c (aarch64_conds): Add SVE names.

(aarch64_print_operand): Print alternative condition names in

a comment.

2016-09-21 Richard Sandiford <[email protected]>

* aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)

(OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)

(OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)

(OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)

(OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)

(OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)

(OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)

(OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)

(OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)

(OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)

(OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)

(OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)

(OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)

(OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)

(OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)

(OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)

(OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)

(OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)

(OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)

(OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)

(OP_SVE_XWU, OP_SVE_XXU): New macros.

(aarch64_feature_sve): New variable.

(SVE): New macro.

(_SVE_INSN): Likewise.

(aarch64_opcode_table): Add SVE instructions.

* aarch64-opc.h (extract_fields): Declare.

* aarch64-opc-2.c: Regenerate.

* aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.

* aarch64-asm-2.c: Regenerate.

* aarch64-dis.c (extract_fields): Make global.

(do_misc_decoding): Handle the new SVE aarch64_ops.

* aarch64-dis-2.c: Regenerate.

2016-09-21 Richard Sandiford <[email protected]>

* aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)

(FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New

aarch64_field_kinds.

* aarch64-opc.c (fields): Add corresponding entries.

* aarch64-asm.c (aarch64_get_variant): New function.

(aarch64_encode_variant_using_iclass): Likewise.

(aarch64_opcode_encode): Call it.

* aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.

(aarch64_opcode_decode): Call it.

2016-09-21 Richard Sandiford <[email protected]>

* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core

and FP register operands.

* aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)

(FLD_SVE_Vn): New aarch64_field_kinds.

* aarch64-opc.c (fields): Add corresponding entries.

(aarch64_print_operand): Handle the new SVE core and FP register

operands.

* aarch64-opc-2.c: Regenerate.

* aarch64-asm-2.c: Likewise.

* aarch64-dis-2.c: Likewise.

2016-09-21 Richard Sandiford <[email protected]>

* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP

immediate operands.

* aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.

* aarch64-opc.c (fields): Add corresponding entry.

(operand_general_constraint_met_p): Handle the new SVE FP immediate

operands.

(aarch64_print_operand): Likewise.

* aarch64-opc-2.c: Regenerate.

* aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)

(ins_sve_float_zero_one): New inserters.

* aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.

(aarch64_ins_sve_float_half_two): Likewise.

(aarch64_ins_sve_float_zero_one): Likewise.

* aarch64-asm-2.c: Regenerate.

* aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)

(ext_sve_float_zero_one): New extractors.

* aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.

(aarch64_ext_sve_float_half_two): Likewise.

(aarch64_ext_sve_float_zero_one): Likewise.

* aarch64-dis-2.c: Regenerate.

2016-09-21 Richard Sandiford <[email protected]>

* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE

integer immediate operands.

* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)

(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)

(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.

* aarch64-opc.c (fields): Add corresponding entries.

(operand_general_constraint_met_p): Handle the new SVE integer

immediate operands.

(aarch64_print_operand): Likewise.

(aarch64_sve_dupm_mov_immediate_p): New function.

* aarch64-opc-2.c: Regenerate.

* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)

(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.

* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...

(aarch64_ins_limm): ...here.

(aarch64_ins_inv_limm): New function.

(aarch64_ins_sve_aimm): Likewise.

(aarch64_ins_sve_asimm): Likewise.

(aarch64_ins_sve_limm_mov): Likewise.

(aarch64_ins_sve_shlimm): Likewise.

(aarch64_ins_sve_shrimm): Likewise.

* aarch64-asm-2.c: Regenerate.

* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)

(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.

* aarch64-dis.c (decode_limm): New function, split out from...

(aarch64_ext_limm): ...here.

(aarch64_ext_inv_limm): New function.

(decode_sve_aimm): Likewise.

(aarch64_ext_sve_aimm): Likewise.

(aarch64_ext_sve_asimm): Likewise.

(aarch64_ext_sve_limm_mov): Likewise.

(aarch64_top_bit): Likewise.

(aarch64_ext_sve_shlimm): Likewise.

(aarch64_ext_sve_shrimm): Likewise.

* aarch64-dis-2.c: Regenerate.

2016-09-21 Richard Sandiford <[email protected]>

* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL

operands.

* aarch64-opc.c (aarch64_operand_modifiers): Initialize

the AARCH64_MOD_MUL_VL entry.

(value_aligned_p): Cope with non-power-of-two alignments.

(operand_general_constraint_met_p): Handle the new MUL VL addresses.

(print_immediate_offset_address): Likewise.

(aarch64_print_operand): Likewise.

* aarch64-opc-2.c: Regenerate.

* aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)

(ins_sve_addr_ri_s9xvl): New inserters.

* aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.

(aarch64_ins_sve_addr_ri_s6xvl): Likewise.

(aarch64_ins_sve_addr_ri_s9xvl): Likewise.

* aarch64-asm-2.c: Regenerate.

* aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)

(ext_sve_addr_ri_s9xvl): New extractors.

* aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.

(aarch64_ext_sve_addr_ri_s4xvl): Likewise.

(aarch64_ext_sve_addr_ri_s6xvl): Likewise.

(aarch64_ext_sve_addr_ri_s9xvl): Likewise.

* aarch64-dis-2.c: Regenerate.

2016-09-21 Richard Sandiford <[email protected]>

* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE

address operands.

* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)

(FLD_SVE_xs_22): New aarch64_field_kinds.

(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.

(get_operand_specific_data): New function.

* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,

FLD_SVE_xs_14 and FLD_SVE_xs_22.

(operand_general_constraint_met_p): Handle the new SVE address

operands.

(sve_reg): New array.

(get_addr_sve_reg_name): New function.

(aarch64_print_operand): Handle the new SVE address operands.

* aarch64-opc-2.c: Regenerate.

* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)

(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)

(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.

* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.

(aarch64_ins_sve_addr_rr_lsl): Likewise.

(aarch64_ins_sve_addr_rz_xtw): Likewise.

(aarch64_ins_sve_addr_zi_u5): Likewise.

(aarch64_ins_sve_addr_zz): Likewise.

(aarch64_ins_sve_addr_zz_lsl): Likewise.

(aarch64_ins_sve_addr_zz_sxtw): Likewise.

(aarch64_ins_sve_addr_zz_uxtw): Likewise.

* aarch64-asm-2.c: Regenerate.

* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)

(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)

(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.

* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.

(aarch64_ext_sve_addr_ri_u6): Likewise.

(aarch64_ext_sve_addr_rr_lsl): Likewise.

(aarch64_ext_sve_addr_rz_xtw): Likewise.

(aarch64_ext_sve_addr_zi_u5): Likewise.

(aarch64_ext_sve_addr_zz): Likewise.

(aarch64_ext_sve_addr_zz_lsl): Likewise.