Merge circuitpython 9.2.8 into cionic fork - #7

The waveshare_esp32_s3_zero/mpconfigboard.h
file does not have SPI nor IC2 defined. I suspect this board was built off another board and while the SPI and IC2 definitions were correctly removed from the mpconfigboard.h file, they were accidentally left in the pins.c file. So if you call a board.I2C or board.SPI you get an error even though they show up in 'dir (board)'.

The board does not have any silkscreen for these busses nor are the specifically called out in the schematic.
https://www.waveshare.com/wiki/ESP32-S3-Zero

…main

Translations update from Hosted Weblate

Update pins.c

Currently translated at 100.0% (1015 of 1015 strings)

Translation: CircuitPython/main
Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/en_GB/

…main

Translations update from Hosted Weblate

…hain

fixed download URL (has 14.2 twice in the url)

Currently translated at 100.0% (1015 of 1015 strings)

Translation: CircuitPython/main
Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/de/

Currently translated at 99.6% (1011 of 1015 strings)

Translation: CircuitPython/main
Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/fr/

Currently translated at 99.4% (1009 of 1015 strings)

Translation: CircuitPython/main
Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/es/

Currently translated at 99.9% (1014 of 1015 strings)

Translation: CircuitPython/main
Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/fr/

Currently translated at 51.8% (526 of 1015 strings)

Translation: CircuitPython/main
Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/pl/

Currently translated at 99.7% (1012 of 1015 strings)

Translation: CircuitPython/main
Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/pt_BR/

Currently translated at 56.0% (569 of 1015 strings)

Translation: CircuitPython/main
Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/nl/

…boot

Fixes REPL not booting on heltec_esp32s3_wifi_lora_v3

…main

Translations update from Hosted Weblate

I added a port-specific module, os.urandom() to ports/analog. Now
users can generate random numbers from the TRNG hardware. The following
code generates 3 random numbers and prints them in hex:

import os
print(os.urandom(3).hex())

Files I modiied:
* ports/analog/Makefile: added INC and SRC for TRNG
* ports/mpconfigport.mk: enabled CIRCUITPY_RANDOM
* ports/analog/common-hal/os/__init__.c: implemented common_hal_os_urandom()
* ports/analog/supervisor/port.c: initialized the TRNG object

Add os.urandom to ports/analog

Currently translated at 52.4% (532 of 1014 strings)

Translation: CircuitPython/main
Translate-URL: https://hosted.weblate.org/projects/circuitpython/main/pl/

…main

Translations update from Hosted Weblate

This is the latest upstream commit. There were many changes in the
past the 3 months since the last submodule update. In particular,
there were some fixes for descriptor parsing and better stability
when devices are unplugged. See issue adafruit#10556.

(as suggested by tannewt in issue adafruit#10556)

As suggested by tannewt in PR adafruit#10559, this turns off codeop for
Feather M0 and errno for the Metro M0 and Redboard Turbo. This is
trying to free up enough space to fit the latest TinyUSB and
Pico-PIO-USB submodule updates.

Add `synthio.MidiTrack.tempo` property

Update TinyUSB submodule commit

…_main

update frozen libraries main

allow HID usage of zero; at least one device does this

…ssif boards

…pressif-boards

Scale current duration when `MidiTrack.tempo` is set

…nsistent

Added mono to stereo conversion and panning to `audiomixer.Mixer`

shrink overflowing boards after adafruit#10529

fix busio.UART.Parity documentation indentation

…upstream