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1. branch-prediction-simulator branch-prediction-simulator Public

   A branch prediction simulator that models how modern CPUs predict branch instructions. It evaluates multiple branch predictor algorithms using offline branch traces, compares predictions against ac…

   C++

2. SRAM-Func-Verification-UVM SRAM-Func-Verification-UVM Public

   A UVM-based testbench for verifying an AHB-SRAM controller, featuring randomized, coverage-driven tests that ensure correctness for all data widths and power-efficient SRAM operation, as described …

   SystemVerilog

3. APB-Peripheral-Subsystem-Verification APB-Peripheral-Subsystem-Verification Public

   A comprehensive SystemVerilog/UVM testbench verifying an AMBA APB Subsystem containing UART, SPI, and I2C controllers.

   SystemVerilog 1

4. mips-5stage-pipelined-rtl mips-5stage-pipelined-rtl Public

   RTL implementation of a classic 5-stage MIPS pipelined processor including fetch, decode, execute, memory, and writeback stages.

   SystemVerilog

5. quadcore-mesi-cache-coherence-rtl quadcore-mesi-cache-coherence-rtl Public

   RTL implementation of a quad-core MESI cache coherence protocol using SystemVerilog. The design models four processor caches connected through a shared bus.

   SystemVerilog

6. HDLBits-Solutions HDLBits-Solutions Public

   HDLBits is considered by many as the leetcode for HDL :) It is a repo of many circuit design exercises. I will capture my solutions in this repo. Feel free to snoop around and star the repo if it h…

   Verilog