Electronic & Information Engineering Undergraduate at Imperial College London
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RISCV-CPU-Design
RISCV-CPU-Design PublicForked from Maximilian-Adam/Team04-RISCV-Proj
RISCV-V 32I CPU designed as part of the Instruction Set Architecture (ISA) coursework for 2nd year EIE at Imperial College London
SystemVerilog 6
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Caleidos_C_Compiler
Caleidos_C_Compiler PublicForked from Maximilian-Adam/Caleidos_C_Compiler
C90 to RISCV Compiler written in C++
C++
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Accelither
Accelither PublicForked from Maximilian-Adam/InfoProc_Proj
Repo for Information Processing Project
Verilog
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