Experimenting with RISC-V, FPGAs etc.
I am a PhD student at the University Freiburg researching on SBST generation for RISC-V.
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cell-aware-spice-simulation
cell-aware-spice-simulation PublicScientific tool to generate fault cell-aware models from SPICE cell simulations
Python 1
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reconfigurable-scan-network-insertion
reconfigurable-scan-network-insertion PublicScientific tool to insert Reconfigurable Scan Networks (RSN) into synthesized circuits to make them testable
Python
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vscode-vt100-syntax-highlight
vscode-vt100-syntax-highlight PublicThis is a Visual Studio Code extension to display and edit VT100 colors and styles in the text editor. A preview and export functionality enable additional workflows for terminal logs and files wit…
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