- pulp-platform on git
- pulpissimo on original git : the microcontroller architecture of the more recent PULP chips, part of the ongoing "PULP platform" collaboration between ETH Zurich and the University of Bologna - started in 2013.
- pulp_IAMROOT on study archive git⭐
- PULPissimo_IAMROOT on study archive git⭐
- westerndigitalcorporation/swerv_eh1 : A directory of Western Digital’s RISC-V SweRV Cores
- Papers with regards to RISC-V in Google Scholar search results
- Program Synthesis Through Reinforcement Learning Guided Tree Search
- The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes
- A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices
- Conquering the Complexity Mountain: Full-stack Computer Architecture teaching with FPGAs
- RISC-V Workshop in Chennai Proceedings, JULY 19, 2018
- RISC-V Day in Shanghai Proceedings, JULY 5, 2018
- RISC-V Workshop in Barcelona Proceedings, MAY 8, 2018
- 7th RISC-V Workshop Proceedings, DECEMBER 9, 2017
- 6th RISC-V Workshop Proceedings, MAY 28, 2017
- 5th RISC-V Workshop Proceedings, DECEMBER 11, 2016
- 4th RISC-V Workshop Proceedings, JULY 25, 2016
- 3rd RISC-V Workshop Proceedings, JANUARY 23, 2016
- 2nd RISC-V Workshop Proceedings, JULY 29, 2015
- 1st RISC-V Workshop Proceedings, JANUARY 14, 2015
- rocket-chip/src/main/
- RISC-V "Rocket Chip" SoC Generator in Chisel - 1st RISC-V Workshop
- [2016] QEMU Support for the RISC-V Instruction Set Architecture by Sagar Karandikar
- Rocket Chip Generator
- Simple RISC-V 3-stage Pipeline in Chisel⭐
- VLSI Systems Design_2011
- VLSI Systems Design_2017
- Rocket Chip on FPGAs
- SiFive's Freedom platforms
- Artix-7 35T Arty FPGA Evaluation Kit
- riscv-sodor
- learning-journey