Labs of MEL G642 (VLSI Architecture), a higher degree chip design course

Basics of Verilog HDL, task is to test functions of each verilog operator and display its results

Focused on efficient adders, task is to design 16,32 and 64 bit signed and unsigned Ripple Carry Adders, a 32 bit signed Redundant Carry Adder, a 64 bit heirarchical Carry Lookahead Adder. Then synthesise and compare LUTs, Power consumed and Delay

Focused on 32 bit general purpose combinatorial shifter with left/right arithmetic/logical shift operations. Synthesis and record of LUTs, Power consumed and Delay

Design a Moore FSM controller to control the appliances for room comfort as per specifications, given inputs that are sensitive to temperature change. Then syntheize it for Xilinx FPGA (XC7Z020 CLG484-1) and characterize performance, complexity, delay and power.

Simulate the CORDIC algorithm for 16 iterations and track convergence

Simulate a CISC processor - MIN - as modelled in Nick Tredennick's Microprocesor Logic Design. And run a simple program to load values from memory, operate on them and store them back.

Add a custom instruction to sum all elements in an array. Flowcharts created and control words added to MIN Processor

Simulate Execute stage of a 5 stage RISC V pipelined processor. ISA: RV32I

Simulate MEM stage of a 5 stage RISC V pipelined processor. ISA: RV32I