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1. Commits on Oct 10, 2026

   • Revert "simd: mask_row_window (2-D window, refuse or zero-fill) + bit_sliced_weighted_count"

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   • Revert "mask_row_window: no overflow at extreme columns or widths"

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   • mask_row_window: no overflow at extreme columns or widths

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   • simd: mask_row_window (2-D window, refuse or zero-fill) + bit_sliced_weighted_count

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   • packed/cascade: pin that the two stroke packers agree at 2048 bytes

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   • v2 arm: rustfmt the test-module gate; blackboard entry

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   • v2 arm: gate simd_avx2's own test modules off v2; document the realizations

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   • v2 arm: tests use the facade or gate off v2; SAFETY at the gather call site

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   • simd: x86-64-v2 realization (SSE4.2 without AVX) via the scalar backend

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   • simd: I8x16::saturating_abs no longer needs SSSE3 at run time

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   • docs: fix the 126 rustdoc warnings so docs/nightly passes with -Dwarnings

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   • ci: make the four nightly jobs actually run on nightly; skip cpu_guard under Miri

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   • simd: dot_i8 is an exact signed dot product on both x86 arms

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   • simd: test five x86 256-bit integer methods against scalar references

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   • simd_avx: gate F32x8::mul_add FMA3 body at compile time; witness FMA/F16C

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   • AVX arm: CI row, realization docs

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   • simd_avx.rs: AVX-without-AVX2 realization (P1-P3)

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   • cpu_guard: require AVX2 at startup on every x86_64 build

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   • Record the pre-AVX guard as an optional to-do

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   • cpu_guard: cover every target feature a rustc CPU model can enable

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   • Fix I8x32::saturating_abs SAFETY comment: AVX2 is a caller obligation

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   • Rewrite SAFETY comments that cited a pinned tier as caller obligations

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   • Add I8x16 ops and U8x16 on every SIMD arm; scope cmp_gt outside G7

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   • cpu_guard: mirror LLVM's host-feature gating (Apple AVX-512 state, xsave*)

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   • Add cpu_guard: report a build-vs-CPU mismatch before main instead of SIGILL

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2. Commits on Oct 8, 2026

   • Flag deferred pillars and document Stroke 1's recall

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   • checked_affine: composition holds when both forms succeed; pin a case where only the stepwise form fails

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   • checked_affine: overflow test reaches the i64 narrowing, not the square

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   • PowerSums / CrossPowerSums: checked_affine — power sums of an affine image from the sums alone

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   • hpc::phase: phases in turns, a (cos, sin) LUT with stated error bounds, a drift-free accumulator

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3. Commits on Oct 7, 2026

   • simd: branch-free mask_gather_u32 + gated mask_gather_u32_under

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   • cpu_ops: require FMA for the avxvnni tier; README sweep rate and timing order

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4. Commits on Oct 6, 2026

   • simd_runtime: gate the avxvnni tier on AVX-VNNI and emit the VEX VPDPBUSD

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   • simd: add F64x8 simd_eq/ne/lt/gt to the AVX2 and NEON backends

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5. Commits on Oct 4, 2026

   • Merge pull request #340 from AdaWorldAPI/ccr-f6094d67-h6ulb3

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