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1. Commits on Oct 6, 2026

   • examples: bf16_rne_exhaustive — reproducible check over all 2^32 f32 inputs

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2. Commits on Oct 4, 2026

   • examples: bounded vs wide power-sums benchmark (D-LXC-29)

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3. Commits on Sep 25, 2026

   • hpc::perm: the field as an exposure; one fold over all 4096 cells

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   • examples: ternlog_popcnt_gap_probe — the mask_ternlog_popcount loop shape is not the gap

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4. Commits on Sep 24, 2026

   • hdr: thresholds on demand from an integer σ-lattice

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   • hdr: harvest the rolling floor from lance-graph onto exact moments

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5. Commits on Sep 23, 2026

   • simd: mask_ternlog_popcount / mask_ternlog_any — a 3-input Boolean membership ends in Count/Any with no mask written

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6. Commits on Sep 16, 2026

   • probe: wrong unit, an unsupported bound, and a checked ternlog claim

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   • probe: mark the (S - D) median when it is below its own resolution

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   • probe: the (S - D) median was pooled and unfiltered, labelled per-pass

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   • probe: address four codex findings; withdraw the D-vs-F claim

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   • probe: the "pooled over all passes" line was reading ONE pass

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   • probe: answer the codegen bar the padded tail was chosen for, on aarch64

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   • probe: the tail needs a fixed TRIP COUNT, not intrinsics

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   • probe: document the four timing/gate helpers

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   • probe: measure against the REAL mask_and, with a measured noise floor

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   • probe: does the tail descent pay for the mask-ALGEBRA ops, end to end?

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   • build: default target-cpu becomes `native`; v3 moves to an explicit pin

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   • probes: SAFETY comment on every unsafe block; fallback messages name every gated feature

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   • ternlogq_sparse_reapply_probe: the cfg gate itself now requires avx512vl + avx512dq

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   • ternlogq probes: gate the active main on avx512vl (+dq for vptestmq), not avx512f alone

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   • ternlogq sparse re-apply: chunk-skip zmm/ymm/xmm vs the gather, measured

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   • ternlogq tail: measure padded zmm vs zmm→ymm→xmm descent (AVX-512 only)

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   • probe: the Q2 traffic accounting was wrong — the split is a DISCOUNT, not parity

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   • probe: the NATIVE arm was missing from the arms table (codex P2)

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   • probe: G1 and G2's pending falsifiers, RUN — and G2's answer is tier-dependent

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   • probe: black_box every timed arm — the G1 ratio was inflated 13%, corrected

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   • G1 falsifier ANSWERED: the widening WAS the cost — 6.75x on the re-chain

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   • simd: mask_set_range (T1 gap G6) — the range write two consumers were working around

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7. Commits on Sep 14, 2026

   • probe: does vectorizing r2sleigh's OpColumns scans pay? Measured — mostly no

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   • hex probe: heap gate asserts; U64x8 shift operators get doctests

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   • simd_masking_ops: council fixes for #307 — shift-count guards, sub-span law, accumulate falsifier

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   • Hex-tenant probe: node-span shift arms — n = 17.0 -> 5.7 us (-66 %)

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   • Add mask_shift_morton (D-GTM-1m): the hex neighbour shift as a word-level op

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   • Add the hex-tenant probe (D-GTM-0m): top-down + spread on one Morton-keyed SoA

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